RISC, or Reduced Instruction Set Computer is a type of microprocessor architecture that utilizes a small, highly-optimized set of instructions, rather than a more specialized set of instructions often found in other types of architectures. It is a dramatic departure from historical architectures.
Prime difference between RISC and CISC design is the number and complexity of instructions. CISC designs includes complex instruction sets so as to provide an instruction set that closely supports the operations and data structures used by Higher-Level Languages (HLLs). However, the side effects are not easy to ignore.
In late seventies & early eighties designers started looking at simpler instruction set architectures; ISAs having few and simple instruction sets. Though idea was not to reduce the number of instructions, these ISAs tend to have fewer instructions and hence were called Reduced Instruction Set Architectures. IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2 were first few of the RISC designs.
Certain design features have been characteristics of most RISC processors.
· One Cycle Execution Time: RISC processors have a CPI (clock per instruction) of one cycle.
· Pipelining: A technique that allows simultaneous execution of parts, or stages, of instructions to more efficiently process instructions.
· Large Number of Registers. The RISC design philosophy generally incorporates a larger number of registers to prevent large amounts of interactions with memory
Typical Characteristics of RISC Architecture
a. Simple Instructions. The designers of CISC architectures anticipated extensive use of complex instructions because they close the semantic gap. However, in practice, it turns out that compilers mostly ignore these instructions; the fact has been demonstrated by several empirical studies. Because of these reasons, RISC architectures use simpler instructions. Limited fixed length instructions (typically 4 bytes) are provided. No instructions combine load/store with arithmetic.
b. Few Data types: CISC ISA support a variety of data structures, from simple data types such as integers and characters to complex data structures such as records and structures. Empirical data suggest that complex data structures are used relatively infrequently. RISC supports a few simple data types efficiently and the complex/missing data types are synthesized from them.
c. Simple Addressing Modes: CISC designs provide a large number of addressing modes to support complex data structures as well as to provide flexibility to access operands. However it leads to problems of variable instruction execution times & variable-length instructions. This causes inefficient instruction decoding and scheduling. RISC designs use simple addressing modes and fixed length instructions to facilitate pipelining. Memory-indirect addressing is not provided.
d. Identical General Purpose Registers. RISC designs allow any register to be used in any context, simplifying compiler designs.
e. Harvard Architecture: RISC designs often use a Harvard memory model, where the instruction stream and the data stream are conceptually separated
PIPELINING-UNIQUE FEATURE OF RISC
Typically, after the execution of one instruction is over, execution of next instruction starts. But, processors which support pipelining, the instruction execution time is divided in several stages(machine cycles). As soon as processing of one stage is finished, the machine proceeds with executing the second stage. However, when the stage becomes free it is used to execute the same operation that belongs to the next instruction. The operation of the instructions is performed in a pipeline fashion, similar to the assembly line in the factory process. An example of five pipeline stage is shown below:
By overlapping the execution of several instructions in a pipeline fashion, RISC achieves its inherent execution parallelism which is responsible for the performance advantage over the Complex Instruction Set Architectures (CISC).