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CISC & RISC Architecture

Written By: 

Preeti Jain
RISC VS CISC –  An Example of multiplication of two numbers in memory.
Suppose that the main memory is divided into locations numbered from (row) 1: (column) 1 to (row) 5: (column) 4. The execution unit is responsible for carrying out all computations. However, the execution unit can only operate on data that has been loaded into one of the four registers (A, B, C, or D). Let's say we want to find the product of two numbers - one stored in location 1:3 and another stored in location 4:2 and store back the result to 1:3
 cisc 4.JPG
CISC Approach

CISC design would try to finish the task in the minimum possible instructions by implementing hardware which could understand and execute series of operations. Thus the processor would come with a specific instruction ‘MUL’ in its instruction set. ‘MUL’ will loads the two values from the memory into separate registers, multiplies the operands in the execution unit, and then stores the product in the appropriate location. So, the entire task of multiplying two numbers can be completed with one instruction:

MUL 1:3, 4:2
MUL is referred to as a "complex instruction" as it operates directly on the computer's memory banks and does not require the programmer to explicitly call any loading or  storing functions.
RISC Approach

RISC processors use simple instructions that can be executed within a clock cycle. Thus, ‘MUL’ instruction will be divided into three instructions.

i)             "LOAD," which moves data from the memory bank to a register,
ii)             "PROD," which finds the product of two operands located within the registers, and
iii)            "STORE," which moves data from a register to the memory banks.
In order to perform the task, a programmer would need to code four lines of assembly:
LOAD A, 1:3
LOAD B, 4:2
STORE 1:3, A
1. RISC design uses more lines of code and hence, more RAM is needed to store the assembly level instructions. Also, the compiler must also perform more work to convert a high-level language statement into code of this form.

2. Since each instruction requires only one clock cycle to execute, the entire program will execute in approximately the same amount of time as the multi-cycle "MUL" command.

3. RISC "reduced instructions" require less transistors of hardware space than the complex instructions, leaving more room for general purpose registers.

4. As all of the instructions execute in a uniform amount of time (i.e. one clock), pipelining is possible.

5.  Separating the "LOAD" and "STORE" instructions actually reduces the amount of work that the computer must perform. After a CISC-style "MUL" command is executed, the processor automatically erases the registers. If one of the operands needs to be used for another computation, the processor must re-load the data from the memory bank into a register. In RISC, the operand will remain in the register until another value is loaded.


Does RISC mean anything like "It has less number of instruction set than CISC". And so why its is called as RISC....?

RISC has reduced number  instruction set although it requires a combination of many instructions to perform a task that would otherwise require one instruction in the CISC.

Also what does HAL and Semantic gap mean....?. Can you elobrate a liitle more about those two things....?

Thanks for the valuable information shared.

Last couple of lines are confusing.

CISC has less no.of instructions but each instruction a microcodes will be executed.Is that what you mean by large no.of instructions?

Very helpful study material..

What are a few instructions that aren't supported by RISC but are supported by CISC? Expand information as well if you don't mind. Thanks.

For example, if we were to multiply two numbers “a” and “b”, a simple complex instruction “MULT” would suffice for CISC but the same instruction would need more than one instruction in RISC since loading "a" and "b" into register would need to be explicit before performing the MULT instruction.


MULT 2:3, 5:2 ; where 2:3 = a, and 5:2 = b


LOAD A, 2:3
LOAD B, 5:2
STORE 2:3, A


Excelent article!
I've used it in a class and shared this link with the students.

Thank you!

Very nice ass
Wrong information Apple is the best. Intel sucks.

very nice and very cheap good work my friend


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