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Significance of the clock polarity and phase:
Another pair of parameters called clock polarity (CPOL) and clock phase (CPHA) determines the edges of the clock signal on which the data are driven and sampled. In addition to setting the clock frequency, the master must also configure means adjusts or sets the clock polarity (CPOL) and phase (CPHA) with respect to the data. Since the clock serves as synchronization of the data communication, there are four possible modes that can be used in an SPI protocol, based on this CPOL and CPHA.
Clock Polarity (CPOL)
Clock Phase (CPHA)
If the phase of the clock is zero (i.e. CPHA = 0) data is latched at the rising edge of the clock with CPOL = 0, and at the falling edge of the clock with CPOL = 1.
If CPHA = 1, the polarities are reversed. Data is latched at the falling edge of the clock with CPOL = 0, and at the rising edge with CPOL = 1.
The micro-controllers allow the polarity and the phase of the clock to be adjusted. A positive polarity results in latching data at the rising edge of the clock. However data is put on the data line already at the falling edge in order to stabilize. Most peripherals, which can only be slaves, work with this configuration. If it should become necessary to use the other polarity, transitions are reversed.
APPLICATIONS OF SPI
The full duplex capability makes SPI very efficient for master/slave applications. Some devices use the full-duplex mode to implement an efficient, swift data stream for applications such as digital audio, digital signal processing, or telecommunications channels. SPI is used to talk to variety of peripherals, such as
Sensors: Temperature, pressure, ADC, touch-screens, video game controllers
Control devices: Audio coding and decoding, digital potentiometers, DAC.
Camera lenses: Canon EF lens mount
Communications: Ethernet, USB, USART, CAN handheld video games
Memory: Flash and EEPROM
LCD, sometimes even for managing image data
Any MMC or SD card (including SDIO variant)
For high performance systems, FPGAs sometimes use SPI to interface as a slave to a host, as a master to sensors, or for flash memory used to bootstrap if they are SRAM-based.
JTAG is essentially an application stack for a three-wire SPI flavor, using different signal names. SGPIO is essentially another (incompatible) application stack for SPI designed for particular backplane management activities SGPIO uses 3-bit messages.