3.1.2: Counters and Timers:
Many microcontroller applications require the counting of external events such as frequency of pulse train, or the generation of precise internal time delays between computer actions. Three sixteen bit counters named T0,T1and T2 are provided for general use of the programmer. Each counter may be programmed to count internal clock pulses acting as a timer or program to count external pulses as a counter.
The counters are divided into eight bit registers called the timer low (TL0, TL1) and high (TH0, TH1) bytes. All counter actions is controlled by bit status in the timer mode control registers TMOD, the timer/counter control register TCON, and certain program instructions.
TMOD is dedicated entirely to the timer and can be considered to be two duplicate 4 bit registers, each of which controls the action of one of the timer. TCON has the control bits and flags for the timer in the upper nibble, control bits and flags for external interrupts in the lower nibble.
Timer Counter Interrupts:
The timers have been included on the chip to relieve the processor of timing and counting chores. When the program wished to count a certain number of internal pulses or external events, a number is placed in one of the counters. The number represents the maximum countless the decide count, plus 1.The counter increments from the initial number to the maximum and then roles over to 0 on the final pulse and also set a timer flag. The flag condition may be tested by an instruction to tell the program that the count has been accomplished, or the flag may be used to interrupt the program.
If a counter is programmed to be a timer, it will count the internal clock frequency of the oscillator divided by 12d. The resultant timer clock is gated to the timer. The bit TRX in the TCON register must be set to one (timer run), and the gate counter is configured as a timer, then the timer pulses are gated to the counter by the bit and gate bit or the external input bits INT.
Timer Modes of Operation:
The timers may be operated in one of the four modes that are determined by the mode bits. M1 and M0 in the TMOD register.
Timer mode 0:
Setting timer X mode bits to 00B in the TMOD register results in using the THX register as an eight bit counter and TLX as a five bit counter; pulse input is divided by 32d in TL so that the TH counts the original oscillator reduced by a total 384d.
Timer mode 1:
Mode 1 is similar to mode 0 except TLX is configures as a full 8 bit counter, When the mode bits are set to 01B in the TMOD. The timer flag would be set in 1311 seconds using a 6MHz crystal.
Timer mode 2:
Setting the mode bits to 10b in the TMOD configures the timer to use only the TLX counter as an eight bit counter. THX is used to hold a value that is loaded into TLX every time TLX overflows from FFh to 00h. The timer flag is also set when TLX overflows. This mode exhibits and auto reloaded feature: TLX will count up from the number in THX, overflow, and be initialized again with the contents of THX.
Timer mode 3:
Timer 0 and 1 may be programmed to be in mode 0.1,2 independently of a similar mode for the other timer. This is not true for mode3; the timer does not operate independently if mode 3 is chosen for timer0. Placing timer 1 in mode3 causes it to stop counting; the control bit TRI and the timer flag TF1 are then used by timer 0. Timer 0 in mode 3 becomes two completely separate eight bit counters. TL0 is controlled by the gate arrangement and sets the timer flag TF0 whenever it overflows from FFh to 00h. TH0 receives the timer clock (the oscillator divided by 12) under the control of TRI only and set the TF1 flag when it overflows.
Timer 1 may be still used in modes 0,1 or 2 while timer 0 is on mode 3 with one important exception: the timer 1 will generate no interrupts while timer 0 is using the TF1 overflow flags. Switching timer 1 to mode 3 will stop it and hold whatever count is in timer1.
The only difference between counting and timing in the source of the clock pulses when used as a timer, the clock pulses are sourced from the oscillator through the divide by 12d circuit: when use as counter pint T0 supplies pulses to counter 0 and pin T1 to counter1. Each high and low states of the input pulse must be held constant for at least one machine cycle to ensure reliable counting.
Interrupts are hardware signals that force a program to call a subroutine. Interrupts take up the processor time only when the action by the program is needed. Interrupts are often the only way in which real time programming can be done successfully.
Interrupts may be generated by internal chip operation or by external sources. Any interrupt can cause the microcontroller to perform a hardware call to an interrupt handling subroutine that is located at a pre determined absolute address in the program memory. Five interrupts are provided in the 8051. Three of these are generated automatically by interrupt (R1 or T1). Two interrupts are triggered by external signals provided by circuitry that is connected to pins INT0 and INT1.
All interrupts are under the control of the program. The programmer is able to alter the control bits in the Interrupt Enable register (IE), the Interrupt Priority register (IP) and the Timer Control register (TCON). The program can block all or any of the combinations of the interrupt from acting on the program by suitable setting or clearing of these registers. After the interrupts has been handled by the interrupt subroutine, which is placed by the programmer in the interrupt location in the program memory, the interrupt program must resume operation at the instruction where the interrupt take place. Program resumption is done by storing the interrupted PC address on the stack in ram before changing the PC to the interrupt address in ROM. The PC address will be stored from the stack after an RETI instruction is executed at the end of the interrupt subroutine.
Timer Flag Interrupt:
When a counter/timer slashes overflow, the corresponding timer flag TF0 or TF1 is set to one. The flag is cleared to 0 when the resulting interrupt generates a program call to the appropriate timer subroutine in the memory.
Pins INT0 and INT1 are used by external circuitry. Inputs on these pins can set the interrupt flags IE0 and IE1 in the TCON register to 1 by two different methods. The IEX flag may be set when the INTX pin reached a low level or the flags may be set when a high to low transition takes place on the INTX pin. Bits INT0 and INT1 in TCON program the INTX pins for low level interrupt when set to 0 and program the INTX pins for transition interrupt when set to 1. Flags IEX will be reset when the processor accepts the transition generated interrupt and the interrupt subroutine is accessed. The external circuits must remove the low level before an RETI is executed.
This can be considered as the ultimate interrupt as the program cannot block the action of the voltage at the RST pin. This type of interrupt is often called non maskable interrupt (NMI). Unlike other interrupts, the PC is not stored for later program resumption.
The IE register holds the programmable bits that can enable or disable all the interrupts as a group, or if the group is enabled, each individual interrupt source can be enabled or disabled. The IP register bits, may be set by the program to assign priorities among the various interrupts sources so that more important interrupts can be serviced first.