B.Aditya Raj, Hyderabad, India
5.3.3 Parameters and Resources
TX8 is clocked by one of 16 possible sources. This parameter is set using the Device Editor in PSoC Designer. The Global I/O busses may be used to connect the clock input to an external pin or a clock function generated by a different PSoC block. The 48 MHz clock, the CPU_32 kHz clock, one of the divided clocks, 24V1 or 24V2, or another PSoC block output can be specified as the TX8 clock input. The clock rate must be set to eight times the desired bit transmit rate. One data bit is transmitted out every 10 input clocks.
The output of the transmitter can be routed to the Global Output Bus. The Global Output Bus can then be connected to an external pin or to another PSoC block for further processing.
TX Interrupt Mode
This option determines when an interrupt will be generated for the TX block
In the PSoC devices, digital blocks may provide clock sources in addition to the system clocks. Digital clock sources may even be chained in ripple fashion. This introduces skew with respect to the system clocks.
Data Clock Out
The Data Clock Out signal is a clock signal that corresponds to the Clock input divided by 8. This clock is active only when the data bits are transmitted and will be held high all other times. The rising edge of the clock corresponds to the time when the data is stable and should be sampled. The Data Clock Out signal can be used to facilitate data checking functions such as Cyclical Redundancy Checks.
Table 5.2: Clock sync values and their uses
Interrupt Generation Control
The following two parameters Interrupt API and Int Dispatch Mode are only accessible by setting the Enable Interrupt Generation Control check box in PSoC Designer. This is available under Project > Settings... > Device Editor.
The Interrupt API parameter allows conditional generation of a User Module’s interrupt handler and interrupts vector table entry. Select "Enable" to generate the interrupt handler and interrupt vector table entry. Select "Disable" to bypass the generation of the interrupt handler and interrupt vector table entry. If the Receive Command Buffer is to be used then the Interrupt API parameter should be set to "Enable". Properly selecting whether an Interrupt API is to be generated is recommended particularly with projects that have multiple overlays where a single block resource is used by the different overlays.
The TX8 User Module uses a single block block, designated "TX", which can map freely onto any of the Digital Communication PSoC blocks.
5.3.4 Application Programming Interface
The Application Programming Interface (API) routines are provided as part of the user module to allow the designer to deal with the module at a higher level. This section specifies the interface to each function together with related constants provided by the "include" files.
Table 5.3: Low level Tx8 API
Table 5.4: High level tx8 API
5.3.5 Example Transmission Code in C
5.4 RX8 USER MODULE
5.4.1 Features and Overview
· Burst rates up to 6 Mbits/second.
· RS-232 data-format compliant with framing consisting of start, optional parity, and stop bits.
· Serial data format with even, odd, or no parity.
· Optional interrupt receive register full condition.
· Automatic framing, overrun, and parity error detection.
The RX8 User Module is a RS-232 data-format compliant 8-bit serial receiver with programmable clocking and selectable interrupt or polling control operation. The format of the received data consists of a start bit, an optional parity bit, and a trailing stop bit. Receiver firmware is used to initialize the device, read the received byte, and detect error conditions.
Figure 5.4: Rx8 block diagram
5.4.2 Functional Description
The RX8 User Module implements a serial receiver. The RX8 maps onto a single PSoC block designated "RX" in the PSoC Designer Device Editor. It uses the Buffer, Shift and Control registers of a digital communications type PSoC block.
The Control register is initialized and configured using the RX8 User Module firmware Application Programming Interface (API) routines. Initialization of the RX8 consists of setting the parity, optionally enabling the interrupt on the Rx Register Full condition, and then enabling the receiver.
When a start bit is detected on the RX8 input, a divide-by-eight bit clock is started and synchronized to sample the data in the center of the received bits. On the rising edge of the next eight-bit clocks, the input data is sampled and shifted into the Shift register. If parity is enabled, the next bit clock samples the parity bit. The sampling of the stop bit, on the next clock, results in the received data byte transfer to the Buffer register and the triggering of one or more of the following events:
- Rx Register Full bit in the Control register is set, and if the interrupt for the RX8 is enabled, then the associated interrupt is triggered.
- If the stop bit is not detected at the expected bit position in the data stream, then the Framing Error bit in the Control register is set.
- If the Buffer register has not been read, before the stop bit of the currently received data, then the Overrun Error bit in the Control register is set.
- If a parity error was detected, then the Parity Error bit is set in the Control register.
5.4.3 Parameters and Resources
RX8 is clocked by one of 16 possible sources. The Global I/O busses may be used to connect the clock input to an external pin or a clock function generated by a different PSoC block. The 48 MHz clock, the CPU_32 kHz clock, one of the divided clocks, 24V1 or 24V2, or another PSoC block output can be specified as the RX8 clock input. The clock rate must be set to eight times the desired bit receive rate.
As a general rule, input through desired bus option to a source of asynchronous data. Using a global bus, the input can be connected to one of the external pins.
In the PSoC devices, digital blocks may provide clock sources in addition to the system clocks. Digital clock sources may even be chained in ripple fashion. This introduces skew with respect to the system clocks. These skews are more critical in the CY8C29/27/24/22/21xxx and CY8CLED04/08/16 PSoC device families because of various data-path optimizations, particularly those applied to the system busses. This parameter may be used to control clock skew and ensure proper operation when reading and writing PSoC block register values. Appropriate values for this parameter should be determined from the following table.
This parameter allows the Input signal to be routed to one of the row busses. This signal along with the Data Clock Out can be used to facilitate data verification functions such as Cyclical Redundancy Checks.
Data Clock Out
This parameter allows the bit clock in SPI Mode 3 to be routed to one of the row busses. The bit clock is the Clock input divided by eight. The rising edge of the Data Clock Out signal corresponds to the time when the data is stable and should be sampled. Use the signal along with the RX Output to use data verification functions such as Cyclical Redundancy Checks.
Rx Cmd Buffer
This parameter enables the receive command buffer and firmware used for command processing. The UART RX interrupt must be enabled for the command buffer to operate.
Rx Buffer Size
This parameter determines how many RAM locations are reserved for the receive buffer. The largest command that can be received is one less than the buffer size selected, since the string must be null terminated. This parameter is only valid when the RxCmdBuffer is enabled and the UART RX interrupt is enabled.
This parameter allows the user to invert the RX input signal.
This parameter selects the character that signals the end of a command. When received, a flag is set signaling a complete command has been received. Once this flag is set, additional characters are no longer accepted until the cmdReset () function is called.
This parameter selects the character used to delimit the command and parameters in the command receiver buffer. For example, if the Param_Delimiter is set to a space character (32), each substring separated by a space would be a parameter. Given the string `cmd foo bar c`, the parameters would be `cmd`, `foo`, `bar`, and `c`. Each call of szGetParam() returns a pointer to the next substring in order of placement from left to right as a null terminated string.
Ignore Chars Below
This parameter enables characters below a set value to be ignored by the receive buffer. The characters will be received, but will not be added to the receive buffer. This parameter is only valid when the RxCmdBuffer is enabled and the UART RX interrupt is active.
5.4.4 Application Programming Interface
The Application Programming Interface (API) routines are provided as part of the user module to allow the designer to deal with the module at a higher level. This section specifies the interface to each function together with related constants provided by the "include" files. The API routines allow programmatic control of the RX8 User Module. The following tables list the low level and high level RX8supplied API functions.
Table 5.5: Low level Rx8 API
Table 5.6: High level Rx8 API
5.4.5 Sample Firmware Source Code
5.5 CMPLP USER MODULE (Low Power Comparator)
5.5.1 Features and Overview
•Programmable threshold •Direct connection to digital PSoC block and interrupt The CmpLP User Module provides a comparison of an input from the input column MUX against a programmable reference threshold. Its only output is the column comparator bus.
Figure 5.5: CMPLP block diagram
5.5.2 Functional Description
The comparator is based on a low power comparator which is configured in parallel with the opamp in the continuous time block. When the CmpLP is used, the opamp is disabled. The positive input is connected to the input multiplexer. The negative input is connected to the tap of a resistive divider between Vdd and Vss.
The reference value of the comparator is determined by the following equation:
The output polarity follows the inputs (i.e., a positive input greater than the negative input to the comparator results in a positive output logic level).
The comparator logic output can be switched onto the CompBus to drive the enable inputs of digital blocks, the interrupt controller, and a register that can be read by the CPU.
5.5.3 Parameters and Resources
The COMP block comparator output may be routed to the input bus of the digital PSoC blocks or to an interrupt. The Comp Bus must be enabled to make any of these connections. The Comp Bus parameter must be enabled to enable interrupts.
The threshold is programmable in steps shown in the table below relative to Vdd. When operating from a 5.00V supply, this sets reference values of 0.105V to 3.75V.
The COMP block maps onto any of the continuous time PSoC blocks in the device. However, if the COMP AnalogBus output and the CompBus output are enabled onto their respective buses, care must be exercised to ensure that no other user module tries to drive the same buses.
5.5.4 Application Programming Interface
The Application Programming Interface (API) routines are provided as part of the user module to allow you to deal with the module at a higher level. This section specifies the interface to each function together with related constants provided by the "include" files.
Description: Performs all required initialization for this user module. The comparator output will be driven.
C Prototype: Void CmpLP_Start (void)
Assembler: Call CmpLP_Start
Description: Powers the user module off. The outputs will not be driven.
C Prototype: Void CmpLP_Stop (void)
Assembler: Call CmpLP_Stop
Description: Enables interrupt mode operation.
C Prototype: Void CmpLP_EnableInt (void)
Assembler: call CmpLP_EnableInt
Description: This function checks the status of the comparator outs stored in CMP_CR0.
C Prototype: BYTE CmpLP_PollOutput (void)
Mov [bComparatorState], A
5.5.5 Sample Firmware Source Code
// C main line
#include <m8c.h> // part specific constants and macros
#include "PSoCAPI.h" // PSoC API definitions for all User Modules
Void main ()
// DigBuf_1_EnableInt ();
PRT1DR = 0x03;
PRT1DR = 0x00;
Void delay_sec (int sec)
int i, j, secd;
for (secd=0; secd<=sec; secd++)
for (i=0; i<=2; i++)
for (j= 0; j<=20400; j++)