ALOGORITHM FOR LOW POWER LFSR
As discussed in the previous section LFSR is used to generate test patterns for BIST. In this, test patterns are generated externally by LFSR, which is inexpensive and high speed LFSR is a circuit consists of flip-flops in series. LFSR is shift register where output bit is an XOR function of input bits. The initial value of LFSR is called seed value. LFSR's seed value has a significant effect on energy consumption. . The output that influence the input are Called tap. A LFSR is represented by as polynomial, which is also known as characteristic polynomial used to determine the feedback taps, which determine the length of random pattern generation. The output of LFSR is combination of I's and O's. A common clock signal is applied to all flip-flops, which enable the propagation of logical values from input to output of flip-flops. Increasing the correlation between bits reduces the power dissipation. This can be achieved by adding more number of test vectors, which decreases the switching activity. LFSR is characterized by the polynomial by its characteristics polynomial and inverse of characteristics polynomial is generated polynomial.
In this approach the 3 intermediate test vectors are generated between every two successive vectors (say TI, T2). The total number of signal transition occurs between these 5 vectors are equivalent to the number of transition occurs between the 2 vectors. Hence the power consumption is reduced. Additional circuit is used for few logic gates in order to generate 3 intermediate vectors. The 3 intermediate vectors (Ta, Tb, Tc) are achieved bydown includes logic circuit design for propagation either the present or next state of flip-flop to second level of hierarchy. Second level of hierarchy is implementing Multiplexed (MUX) function i.e. selecting two states to propagate to output as shown in flow: The EDA tool is used in which conventional and low power LFSR is coded in Verilog hardware descriptive language and a seed value is given (010010100101101011010010100101101011) to the polynomial and primitive value polynomial in LFSR block. The outputs of the 36-bit LFSR are used as the inputs to the c42 ISVAS-85 a benchmark circuit of interrupt controller. In this c432 is used as CUT; the generated code is synthesized in Xilinx Web Pack 9.1 for Spartan 2e device. The hardware summary is obtained for each method implementation log file of Xilinx 9.1 project navigator. The RTL view of LP-LFSR with c432 benchmark circuit is shown in figure 5.
V.RESULTS AND CONCLUSION
The results obtained from the Xilinx 9.1 implementation with the device xc3s200-4pq208 in which, we have generated VCD file after the post simulation. Xpower is used to calculate the with the simulation file. Results are obtained for each case and comparison of power dissipation is made on the basis of reports is give in table 1 and shown in figure 6.
Type and power
Battery capacity (mA)
Battery Life (hours)
TABLE.1 POWER DISSIPATION CONVENTIONAL AND LOW POWERM LFSR
It is observed that the total power consumed in modified LFSR is 46% less than the power consumed with normal LFSR and output dynamic power is decreased by 44.6 %. It is concluded that low power LFSR is very useful for BIST Implementation in which the CUT may be Combinational, sequential and memory circuits. Using low power LFSR technique we can further decrease the power in BIST implementation.