Serial Peripheral Interface is a synchronous, full-duplex protocol. SPI is also known as “3-wire interface” protocol because it needs 3 communication lines named MISO, MOSI and SCK. SPI protocol needs two devices for communication. One of them is considered as a MASTER and another one as a SLAVE. AVR microcontrollers contain both MASTER and SLAVE interface on single chip. Thus, a microcontroller can work as both master and slave device.
Besides the MISO, MOSI and SCK pins, the SS is also included in SPI system. This pin is used to select slave device. Following table explains functionality of these pins:
How SPI works:
The SPI is synchronous data transfer protocol, so clock pulse is needed to synchronize both master and slave device. The clock pulse is generated from master side. The SCK pin of master provides clock pulse to slave device.
To make any device as master, the SS pin must be set as high. If it is configured as an output pin, then it made high using the software. If the SS is considered as input pin, it should make high externally. In slave mode SS is always an input pin, which should be connected to ground (to make it slave device).
The “MOSI” stands for “master output slave input”. So, the MOSI pin works as output pin for master device and input pin for salve device. Both master and slave devices contain a buffer register, called SPDR. Master transfers one bit from its SPDR to slave device in every clock cycle. It means to send one byte data, 8 clock pulses are needed.
Registers of SPI System:
The SPI system consists three register which are described below:
1. SPCR (SPI control register):
SPIE (SPI Interrupt Enable) - To enable SPI interrupt this is set as high.
SPE (SPI Enable) - SPI system is enabled when this bit is set.
DORD (Data Order) – For DORD=1, LSB will be transmitted first.
For DORD=0, MSB will be transmitted first.
MSTR (Master/Slave Select) – For MSTR=1, to select device as master.
For MSTR=0, to select device as slave.
SPR [1:0] (SPI clock Rate) - This SPR [1:0] and SPI2X bit of SPSR register decides frequency of SCK. The combination of these three bits to select SCK frequency are shown in following table:
2. SPSR (SPI Status REGISTER) :
SPIF (SPI Interrupt Flag) – This bit become set automatically after completion of serial transfer.
WCOL (Write Collision Flag) – This bit is set if SPDR is written during data transfer.
SPI2X (Double SPI Bit) – By setting 1 to this bit SCK frequency become double.
3. SPDR (SPI Data Register) – This is 8-bit data register used to store receive data and transmitting data.
Objective: To interface ATmega32 and Atmega16 microcontroller using SPI protocol. Consider ATmega32 as master and Atmega16 as slave.
The connection of both master and slave microcontrollers are shown in circuit diagram. MOSI pins (pin no.6) of both master and slave are connected. The SCK (pin no 8) pins of both master and slave are connected. SS pin of slave is grounded.
For Master mode:
1. Set SS, MOSI and SCK pin as output pins.
2. Enable MSTR bit to make it master device.
3. Program SPR [1:0] bits to select SCK frequency.
4. Set SPE bit to enable SPI.
5. Copy data in SPDR register to send.
6. Wait until SPI interrupt flag get set.
For slave mode:
1. Select MOSI pin as output and rest pins as input pins.
2. Set SPE to activate SPI.
3. Wait until SPI interrupt flag get set.
4. Receive data from SPDR register.