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Introduction to VHDL & Verilog - DE Part 9

Written By: 

Hari Prasaath K.

In the previous tutorials, boolean functions, boolean expressions, minimization of boolean expressions and implementation of a boolean function into logic gate diagram was discussed. It is possible to minimize a boolean function with less number of boolean variables and implement a logic gate diagram for it manually. But as the number of variables in a boolean function increases, not only its minimization becomes complex, designing a logic gate implementation for it also becomes cumbersome. In such case, computer based design tools are the ultimate resort.

These digital circuit design tools use hardware description language to describe, prototype and test a digital circuit. A Hardware Description Language is a programming language that describes the hardware architecture and functioning of a digital circuit in the form of text. A hardware description language basically describes the relationship between the input signals to a digital circuit and the output signals from it. In this way, it can textually represent any truth table, boolean function or boolean expression. The HDL generally have a syntax that is both readable by humans as well as software tools (design applications).

Hardware Description Languages

Fig. 1: Hardware Description Languages

The design process of a digital integrated circuit using HDL involves the following steps -

1) Design Entry: This is the first step in the designing of a digital integrated circuit. In this step, HDL is used to describe the functionality of the digital circuit. The description can be in the form of truth table, boolean equation, netlist of interconnected logic gates or behavioural models. A large and complex digital circuit may be divided into small functional units or models that are then interconnected with each unit having its own functionality and behaviour.  

2) Logic Simulation: In this step, the digital circuit based on the HDL statements is simulated either as time ordered sequence of input and output signals or in the waveform of the input and output signals. The simulation of the digital circuit is useful in detecting any error in the logical design of the circuit even before its fabrication on a chip. The logic values of the input signals that are used to simulate the digital circuit are called test bench. The test bench is also written in HDL. By simulating the digital design, the errors in the logic of the circuit are detected and the respective HDL statements are then corrected to derive the desired output signals.  

3) Design Synthesis: In this step, the digital circuit is programmatically synthesized as a database of physical components required and their interconnections. The interconnection of physical components of the digital circuit is called netlist. This database can be used to fabricate the circuit either on a silicon chip or as layout on a printed circuit board. The digital database generated by synthesis tools is useful in automating the fabrication of the digital integrated circuit as the actual procedures involved in the implementation of the digital circuit are incorporated within the database.    

4) Timing Verification: The digital circuits must output signals within a desired time limit. There is some propagation delay in the signal when it transits from one logic gate to another. Practically, this propagation delay must be minimized (like by two-level implementation of the boolean functions in the circuit). By time verification, the speed of the digital circuit is confirmed. The process involves checking each signal path and confirm that it is not compromised by the propagation delays. This is the final step before the fabrication of the digital circuit.

5) Fault Simulation: Before the circuit is produced, it is compared with the ideal circuit as initially described in the HDL. The production circuit may not exhibit the same behaviour as the ideal circuit in case there may induce some fault in the circuit. The production circuit must be verified being fault free before shipping. The fault simulation is always done before production to test the internal logic of the integrated circuit.

6) Physical Design: In the process, the digital circuit is fabricated on a silicon chip or PCB inside a clean room. This is the production stage of the circuit. The circuit must be fabricated in a dust free environment. Even a single dust particle can cause fault in the functioning of the circuit.

There are two standard Hardware Description Languages - VHDL and Verilog. VHDL is an abbreviation of VHSIC Hardware Description Language where VHSIC stands for Very High Scale Integrated Circuit. VHDL is a IEEE standard HDL language mandated by Department of Defence. The Verilog is a proprietary HDL language from Cadence Design Systems. The Cadence has transferred the control of Verilog to a consortium of companies and universities known by name - Open Verilog International. The OVI Verilog is developed as an adoption for IEEE standard. The Verilog is simple to use and learn compared to VHDL.

In the next tutorial, learn about arithmetic circuits. The arithmetic circuits are the basic digital circuits that are the part of an arithmetic Logic Unit (ALU) in any Central Processing Unit (CPU). 

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