Image below shows the pin diagram of a 55 timer IC:
The circuit in this project uses an npn transistor T1 to achieve the above objective. 555 timer in monostable configuration is shown in the figure. Pin 2, which is the trigger pin of the IC is connected to the collector of T1. When no signal is present on the base the transistor T1, it is in the cut off state. As a result point “A” is high, thus making the pin 2 high and there is no output at pin 3 of the IC.
Filed Under: 555 Timers, Electronic Projects