This tutorial will teach you how to use the inbuilt ADC of LPC1768 to convert an analog voltage input to a digital number and display in the LCD. Setting up the Environment for the development of ARM cortex M3 is well discussed in this article.
The LPC 1768 is ARM Cortex- M3 based Microcontrollers for embedded application features in low power consumption and a high level of integration. The ARM Cortex M3 is designed in a such way to enhance debug features and a higher level of system integration. It clocks at a CPU frequency of 100 MHz, and incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses for third bus peripherals. The ARM Cortex- M3 CPU have an internal pre-fetch unit to support speculative branching. The peripheral components include 512KB of flash memory, 64kb of data memory, Ethernet MAC, USB OTG, 4 UART’s, 8-channel general purpose DMA controller, 2 SSP Controllers, 10-bit DAC, Quadrature encoder interface, SPI interface, 3 I2C bus interface, 2 input plus 2 outputs I2S bus interface, 4 general purpose timers, ultra-low power Real-Time Clock (RTC) with separate battery supply, and up to 70 general purpose I/O pins, 6-output general purpose PWM. The LPC1768/66/65/64 are pin-compatible with the 100-pin LPC236x ARM7-based Microcontroller series.
Fig. 1: ADC Programming In LPC1768 Prototype
LPC1768 ADC is pretty complex peripheral. It is designed to be flexible enough to accomplish complex tasks. Lets see what ADC is capable to do. Generally speaking LPC1768 ADC have up to 8 multiplexed 12 bit Successive Approximation ADC. ADC module has a separate supply which normally can be connected to general MCU power supply. Also ADC can have external reference source through VREF+ and VREF- that can be brought through dedicated pins. In no special case analog supply voltage may be as reference internally. ADC can be performed in a single or continuous mode for single channel, scan through all channels, externally triggered conversion. There is also an analog watchdog, which can detect if voltage exceed preset threshold values. And of course DMA request based conversions.
As LPC1768 works on 3.3 volts, this will be the ADC reference voltage.
Now the resolution of ADC = 3.3/(2^12) = 3.3/4096 =0.000805 = 0.8mV
POWERING THE ADC:
PCON register bits description:
Bit |
Symbol |
Description |
Reset value |
0 |
– |
Reserved. |
NA |
1 |
PCTIM0 |
Timer/Counter 0 power/clock control bit. |
1 |
2 |
PCTIM1 |
Timer/Counter 1 power/clock control bit. |
1 |
3 |
PCUART0 |
UART0 power/clock control bit. |
1 |
4 |
PCUART1 |
UART1 power/clock control bit. |
1 |
5 |
– |
Reserved. |
NA |
6 |
PCPWM1 |
PWM1 power/clock control bit. |
1 |
7 |
PCI2C0 |
The I2C0 interface power/clock control bit. |
1 |
8 |
PCSPI |
The SPI interface power/clock control bit. |
1 |
9 |
PCRTC |
The RTC power/clock control bit. |
1 |
10 |
PCSSP1 |
The SSP 1 interface power/clock control bit. |
1 |
11 |
– |
Reserved. |
NA |
12 |
PCADC |
A/D converter (ADC) power/clock control bit. |
0 |
13 |
PCCAN1 |
CAN Controller 1 power/clock control bit. |
0 |
14 |
PCCAN2 |
CAN Controller 2 power/clock control bit. |
0 |
15 |
PCGPIO |
Power/clock control bit for IOCON, GPIO, and GPIO interrupts. |
1 |
16 |
PCRIT |
Repetitive Interrupt Timer power/clock control bit. |
0 |
17 |
PCMCPWM |
Motor Control PWM |
0 |
18 |
PCQEI |
Quadrature Encoder Interface power/clock control bit. |
0 |
19 |
PCI2C1 |
The I2C1 interface power/clock control bit. |
1 |
20 |
– |
Reserved. |
NA |
21 |
PCSSP0 |
The SSP0 interface power/clock control bit. |
1 |
22 |
PCTIM2 |
Timer 2 power/clock control bit. |
0 |
23 |
PCTIM3 |
Timer 3 power/clock control bit. |
0 |
24 |
PCUART2 |
UART 2 power/clock control bit. |
0 |
25 |
PCUART3 |
UART 3 power/clock control bit. |
0 |
26 |
PCI2C2 |
I2C interface 2 power/clock control bit. |
1 |
27 |
PCI2S |
I2S interface power/clock control bit. |
0 |
28 |
– |
Reserved. |
NA |
29 |
PCGPDMA |
GPDMA function power/clock control bit. |
0 |
30 |
PCENET |
Ethernet block power/clock control bit. |
0 |
31 |
PCUSB |
USB interface power/clock control bit. |
0 |
Fig. 2: Bit Description Of PCON Register In LPC1768 For Powering ADC
Following reset the PCADC (Power Clock Control Bit to ADC) bit is cleared and the ADC is disabled. The first step is to set PCADC followed by PDN in ADC0CR.
Code snipet:
LPC_SC->PCONP |= (1 << 12); /* Enable CLOCK for internal ADC controller */
SELECTING CLOCK FOR ADC:
By assuming that the main clock for the LPC1768 has been programmed. Each LPC1768 peripheral including the ADC has a clock derived from the main clock as illustrated.
Peripheral Clock Divider
As shown in the below block the frequency of the peripheral clock is determined by two bits in the PCLKSEL registers. ADC is included in PCLKSEL0. With the NXP LPC1768 the peripheral clocks are always active. Following RESET PCLKSEL registers are cleared setting the peripheral clock frequency to CCLK/4 to all the peripherals. The user will have a choice of frequency which can be determined by two bits for each peripherals among the peripheral clock selection registers PCLKSEL0 and PCLKSEL1. By default at reset all values are 00 ie CCLK/4.
00 |
PCLK_peripheral = CCLK/4 |
01 |
PCLK_peripheral = CCLK |
10 |
PCLK_peripheral = CCLK/2 |
11 |
PCLK_peripheral = CCLK/8, except for CAN1, CAN2, |
Fig. 3: Bit Value Of PCLK_Peripheral For Clock Frequency
Bit |
Symbol |
Description |
1:0 |
PCLK_WDT |
Peripheral clock selection for WDT. |
3:2 |
PCLK_TIMER0 |
Peripheral clock selection for TIMER0. |
5:4 |
PCLK_TIMER1 |
Peripheral clock selection for TIMER1. |
7:6 |
PCLK_UART0 |
Peripheral clock selection for UART0. |
9:8 |
PCLK_UART1 |
Peripheral clock selection for UART1. |
11:10 |
– |
Reserved. |
13:12 |
PCLK_PWM1 |
Peripheral clock selection for PWM1. |
15:14 |
PCLK_I2C0 |
Peripheral clock selection for I2C0. |
17:16 |
PCLK_SPI |
Peripheral clock selection for SPI. |
19:18 |
– |
Reserved. |
21:20 |
PCLK_SSP1 |
Peripheral clock selection for SSP1. |
23:22 |
PCLK_DAC |
Peripheral clock selection for DAC. |
25:24 |
PCLK_ADC |
Peripheral clock selection for ADC. |
27:26 |
PCLK_CAN1 |
Peripheral clock selection for CAN1.[1] |
29:28 |
PCLK_CAN2 |
Peripheral clock selection for CAN2.[1] |
31:30 |
PCLK_ACF |
Peripheral clock selection for CAN acceptance filtering.[1] |
Fig. 4: Bit Value and description of PCLK_peripheral in LPC1768
SELECTING THE ADC FUNCTION TO GPIO:
The block diagram below shows the ADC input pins multiplexed with other GPIO pins. The ADC pin can be enabled by configuring the corresponding PINSEL register to select ADC function. When the ADC function is selected for that pin in the Pin Select register, other Digital signals are disconnected from the ADC input pins.
Adc Channel |
Port Pin |
Pin Functions |
Associated PINSEL Register |
AD0 |
P0.23 |
0-GPIO, 1-AD0[0], 2-I2SRX_CLK, 3-CAP3[0] |
14,15 bits of PINSEL1 |
AD1 |
P0.24 |
0-GPIO, 1-AD0[1], 2-I2SRX_WS, 3-CAP3[1] |
16,17 bits of PINSEL1 |
AD2 |
P0.25 |
0-GPIO, 1-AD0[2], 2-I2SRX_SDA, 3-TXD3 |
18,19 bits of PINSEL1 |
AD3 |
P0.26 |
0-GPIO, 1-AD0[3], 2-AOUT, 3-RXD3 |
20,21 bits of PINSEL1 |
AD4 |
P1.30 |
0-GPIO, 1-VBUS, 2- , 3-AD0[4] |
28,29 bits of PINSEL3 |
AD5 |
P1.31 |
0-GPIO, 1-SCK1, 2- , 3-AD0[5] |
30,31 bits of PINSEL3 |
AD6 |
P0.3 |
0-GPIO, 1-RXD0, 2-AD0[6], 3- |
6,7 bits of PINSEL0 |
AD7 |
P0.2 |
0-GPIO, 1-TXD0, 2-AD0[7], 3- |
4,5 bits of PINSEL0 |
Fig. 5: PINSEL register to select ADC function in LPC1768
Code snipet:
LPC_PINCON->PINSEL3|= 0x01<<30;
LPC_PINCON->PINSEL3|= 0x01<<31; /* Select the P1_31 AD0[5] for ADC function */
ADC REGISTERS:
The registers associated with LPC1768 ADC are
-
ADCR-> A/D Control Register: Used for Configuring the ADC
-
ADGDR-> A/D Global Data Register: This register contains the ADC’s DONE bit and the result of the most recent A/D conversion
-
ADINTEN- >A/D Interrupt Enable Register
-
ADDR0 – ADDR7-> A/D Channel Data Register: Contains the recent ADC value for respective channel
-
ADSTAT-> A/D Status Register: Contains DONE & OVERRUN flag for all the ADC channels
ADC REGISTER CONFIGURATION:
ADCR ( ADC Control Register )
Bit |
Symbol |
Description |
Reset value |
7:0 |
SEL |
Selects which of the AD0.7:0 pins is (are) to be sampled and converted. |
0x01 |
15:8 |
CLKDIV |
The APB clock (PCLK_ADC0) is divided by (this value plus one) to produce the clock for the A/D converter. |
0 |
16 |
BURST |
1 The AD converter does repeated conversions at up to 200 kHz |
0 |
20:17 |
– |
Reserved, user software should not write ones to reserved bits. |
NA |
21 |
PDN |
1 The A/D converter is operational. 0 The A/D converter is in power-down mode. |
0 |
23:22 |
– |
Reserved, user software should not write ones to reserved bits. |
NA |
26:24 |
START |
When the BURST bit is 0, these bits control whether and when an A/D conversion is started: |
000 |
27 |
EDGE |
1 Start conversion on a falling edge. 0 Start conversion on a rising edge. |
0 |
31:28 |
– |
Reserved, user software should not write ones to reserved bits. |
NA |
Fig. 6: Bit Value of ADCR Control Register to configure ADC in LPC1768
Code snipet:
LPC_ADC->ADCR = ((1<<SBIT_PDN) | (10<<SBIT_CLCKDIV)); //Set the clock and Power ON ADC module
LPC_ADC->ADCR |= 0x01<<5; /* Select Channel 5 by setting 5th bit of ADCR */
ADC Global Data Register :
The ADC Global Data Register contains the status, result and the channel number of the last converesion. This register is shown for completeness below.
Bit |
Symbol |
Description |
Reset value |
3:0 |
– |
Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |
NA |
15:4 |
RESULT |
When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. |
NA |
23:16 |
– |
Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |
NA |
26:24 |
CHN |
These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1…). |
NA |
29:27 |
– |
Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |
NA |
30 |
OVERRUN |
This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register. |
0 |
31 |
DONE |
This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started. |
0 |
Fig. 7: Bit Value and Description of ADC Global Data Register in LPC1768
Code snipet:
adc_result = (LPC_ADC->ADGDR >> SBIT_RESULT) & 0xfff; /*Read the 12bit adc result*/
Create a project using Keil uvision4 for LPC1768 Microcontroller:
In this section, we will start creating a project in Keil MDK we have already installed Keil µVision and Co-MDK Plug-in + CoLinkEx Drivers required for the CoLinkEx programming adapter. You can start by downloading the project files and kick start your practical experiment.
For more details on interfacing the LCD in 4 bit mode with LPC1768 refer this link.
Project Source Code
###The codes are linked in Description ###
Circuit Diagrams
Project Components
Project Video
Filed Under: ARM
Filed Under: ARM
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