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CISC & RISC Architecture

Written By: 

Preeti Jain

 

In layman terms, computers can be defined as a hierarchical series of metal, silicon and plastic (Hardware) fused with software all around it. These two entities combine to form a powerful machine that can process gigabytes of data in a span of a few seconds. The role played by hardware and software has always been closely studied so as to find which one should play the major part. Major Computer manufacturing firms Apple and Intel have always been arguing on importance of hardware and software in CPU architecture designs. Intel supporters want the hardware to bear more responsibility and software on the easier side. This would impact the hardware designing to be more complex but software coding would be relatively easy. On the other hand, Apple supporters want the hardware to be simple and easy and software to take the major role. Intel’s hardware oriented approach is termed as Complex Instruction Set Computer while that of Apple is Reduced Instruction Set Computer. Let’s have a thorough look on the basics, differences and pros and cons of these two well known CPU architecture designs.

 

Architecture of Central Processing Unit drives its working ability from the instruction set architecture upon which it is designed. Instruction Set Architecture can be defined as an interface to allow easy communication between the programmer and the hardware.  ISA prepares microprocessor to respond to all the user commands like execution of data, copying data, deleting it, editing it and several such and diverse operations. Some major terms that are often used in ISA are:
 
Instruction Set: It is a group of instructions that can be given to the computer. These instructions direct the computer in terms of data manipulation. A typical instruction consists of two parts: Opcode and Operand.
Opcode or operational code is the instruction applied. It can be loading data, storing data etc.
Oprand is the memory register or data upon which instruction is applied.
 
Addressing Modes: Addressing modes are the manner in the data is accessed. Depending upon the type of instruction applied, addressing modes are of various types such as direct mode where straight data is accessed or indirect mode where the location of the data is accessed.
Processors having identical ISA may be very different in organization. Processors with identical ISA and nearly identical organization are still not nearly identical.
CPU performance is given by the fundamental law:
 
An equation representing the fundamental law of CPU time
 
Fig. 1: An Equation Representing the Fundamental Law of CPU Time
 
Thus, CPU performance is dependent upon Instruction Count, CPI (Cycles per instruction) and Clock cycle time. And all three are affected by the instruction set architecture.
 
 
Instruction Count
CPI
Clock
Program
x
 
 
Compiler
x
x
 
Instruction Set Architecture
x
x
x
Microarchitecture
 
x
x
Physical Design
 
 
x
 
This underlines the importance of the instruction set architecture. There are two prevalent instruction set architectures:
Complex Instruction Set Architecture (CISC) : The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction.
Reduced Instruction Set Architecture (RISC): RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program
Subsequent sections will discuss RISC, CISC designs and their characteristics.
 
SEMANTIC GAP
Both RISC and CISC architectures have been developed as an attempt to cover the semantic gap.
A figure explaining development of RISC and CISC architectures as an attempt to cover the semantic gap
 
Fig. 2: A Figure Explaining Development of RISC and CISC Architectures as an Attempt to Cover the Semantic Gap
 
With an objective of improving efficiency of software development, several powerful programming languages have come up, viz., Ada, C, C++, Java, etc. They provide high level of abstraction, conciseness and power. By this evolution the semantic gap grows. To enable efficient compilation of high level language programs, CISC and RISC designs are the two options.
CISC designs involve very complex architectures including a large number of instructions and addressing modes, whereas RISC designs involve simplified instruction set and adapt it to the real requirements of user programs.
 

CISC Architecture

CISC
Prior to RISC, in the early days of the computers, programming was primarily done in assembly language (or machine code) and these promoted powerful and easy to use instructions. Therefore, CPU designers tried to make instructions to do as much work as possible. With the arrival of higher level languages, computer architects also started to create dedicated instructions to directly implement various mechanisms of such languages.
Another goal was to provide every possible addressing mode for every instruction. Since hardware design was more mature than compiler design, designers tend to implement parts of functionality in hardware rather than in a memory constrained compiler alone.
Since the earliest machines were programmed in assembly language and memory was slow and expensive, the CISC philosophy made sense, and was commonly implemented in large computers such as the PDP-11 and the DECsystem 10 and 20 machines. Slowness of memory access prompted designers to create instructions which reduce the frequency of memory access. Also, memory sizes were limited due to which only small programs could be stored in them. This encouraged dense and complex instructions.
After RISC philosophy got its name, this pre-RISC philosophy became retroactively called Complex Instruction Set Computer. CISC processors were designed to simplify compilers and to improve performance under constraints such as small and slow memories.
CISC is intended to ease compiler writing, improve execution efficiency, and to support more complex high level languages. It shifts most of the burden of generating machine instructions to the processor. For example, instead of having to make a compiler write long machine instructions to calculate a square-root, a CISC processor would have a built-in ability to do this.
 
Typical Characteristics of CISC Architecture
Most CISC hardware architectures have several characteristics in common:
·     Complex instruction-decoding logic,
It is driven by the need for a single instruction to support multiple addressing modes.
·     Small number of general purpose registers.
Instructions which operate directly on memory, and only the limited amount of chip space is dedicated for general purpose registers.
·     Several special purpose registers.
Many CISC designs set aside special registers for the stack pointer, interrupt handling, and so on. This can simplify the hardware design somewhat, at the expense of making the instruction set more complex.
·     'Condition code" register
This register reflects whether the result of the last operation is less than, equal to, or greater than zero and records if certain error conditions occur.
 
CISC Processors –Examples
1.      IBM 370/168

 Introduced in 1970, this CISC design is a 32 bit processor with 4 general purpose and 4 64-bit floating point registers.

2.      VAX 11/780
This CISC design is again a 32-bit processor from DEC(Digital Equipment Corporation). It supports large number of addressing modes and machine instructions 
3.      Intel 80486
Launched in 1989, this CISC processor has instructions with their lengths varying from 1 to 11 and had 235 instructions.
 

RISC Architecture

RISC

RISC, or Reduced Instruction Set Computer is a type of microprocessor architecture that utilizes a small, highly-optimized set of instructions, rather than a more specialized set of instructions often found in other types of architectures. It is a dramatic departure from historical architectures.

Prime difference between RISC and CISC design is the number and complexity of instructions. CISC designs includes complex instruction sets so as to provide an instruction set that closely supports the operations and data structures used by Higher-Level Languages (HLLs). However, the side effects are not easy to ignore.
 
In late seventies & early eighties designers started looking at simpler instruction set architectures; ISAs having few and simple instruction sets. Though idea was not to reduce the number of instructions, these ISAs tend to have fewer instructions and hence were called Reduced Instruction Set Architectures. IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2 were first few of the RISC designs.
Certain design features have been characteristics of most RISC processors.
·       One Cycle Execution Time: RISC processors have a CPI (clock per instruction) of one cycle.
·       Pipelining: A technique that allows simultaneous execution of parts, or stages, of instructions to more efficiently process instructions.
·    Large Number of Registers. The RISC design philosophy generally incorporates a larger number of registers to prevent large amounts of interactions with memory
 
Typical Characteristics of RISC Architecture
a.     Simple Instructions. The designers of CISC architectures anticipated extensive use of complex instructions because they close the semantic gap. However, in practice, it turns out that compilers mostly ignore these instructions; the fact has been demonstrated by several empirical studies.  Because of these reasons, RISC architectures use simpler instructions. Limited fixed length instructions (typically 4 bytes) are provided. No instructions combine load/store with arithmetic.
 
b.    Few Data types: CISC ISA support a variety of data structures, from simple data types such as integers and characters to complex data structures such as records and structures. Empirical data suggest that complex data structures are used relatively infrequently. RISC supports a few simple data types efficiently and the complex/missing data types are synthesized from them.
 
c.     Simple Addressing Modes: CISC designs provide a large number of addressing modes to support complex data structures as well as to provide flexibility to access operands. However it leads to problems of variable instruction execution times & variable-length instructions. This causes inefficient instruction decoding and scheduling. RISC designs use simple addressing modes and fixed length instructions to facilitate pipelining. Memory-indirect addressing is not provided.
 
d.     Identical General Purpose Registers.  RISC designs allow any register to be used in any context, simplifying compiler designs.
 
e.    Harvard Architecture: RISC designs often use a Harvard memory model, where the instruction stream and the data stream are conceptually separated
 
PIPELINING-UNIQUE FEATURE OF RISC
Typically, after the execution of one instruction is over, execution of next instruction starts. But, processors which support pipelining, the instruction execution time is divided in several stages(machine cycles). As soon as processing of one stage is finished, the machine proceeds with executing the second stage. However, when the stage becomes free it is used to execute the same operation that belongs to the next instruction. The operation of the instructions is performed in a pipeline fashion, similar to the assembly line in the factory process. An example of five pipeline stage is shown below:
 
A figure explaining the example of five pipeline stage
 
Fig. 3: A Figure Explaining the Example of Five Pipeline Stage
 
By overlapping the execution of several instructions in a pipeline fashion, RISC achieves its inherent execution parallelism which is responsible for the performance advantage over the Complex Instruction Set Architectures (CISC).

 

Example of RISC Architecture

RISC Processors -Examples
1.      Digital Equipment Corporation (DEC) - Alpha
Alpha, originally known as Alpha AXP, is a 64-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC), designed to replace the 32-bit VAX complex instruction set computer (CISC) ISA and its implementations.
2.      Advanced Micro Devices (AMD) 29000
The AMD 29000, often simply 29k, was a popular family of 32-bit RISC microprocessors and microcontrollers developed and fabricated by Advanced Micro Devices(AMD). For quite some time, they were amongst the most popular RISC chips on the market, widely used in laser printers from a variety of manufacturers.
3.      Advanced RISC Machine (ARM).
The ARM is a 32-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by ARM Holdings( earlier known as the Advanced RISC Machine, and before that as the Acorn RISC Machine).
The ARM architecture is the most widely used 32-bit ISA in terms of numbers produced. Their simplicity has led their widespread usage in low power applications like mobiles and embedded electronics.
4.      Atmel AVR.
The AVR is a Modified Harvard architecture 8-bit RISC single chip microcontroller (µC) which was developed by Atmel in 1996.  The AVR was one of the first microcontroller families to use on-chip flash memory for program storage.
5.      Microprocessor without Interlocked Pipeline Stages (MIPS).
MIPS ( MIPS32 – 32 bit and MIPS64 – 64 bit implementation) is a reduced instruction set computer (RISC) instruction set architecture (ISA) developed by MIPS Computer Systems
6.      Precision Architecture – Reduced Instruction Set Computer (PA-RISC).
PA-RISC is an instruction set architecture (ISA) developed by Hewlett-Packard. PA-RISC has been succeeded by the Itanium (originally IA-64) ISA
jointly developed by HP and Intel.
7.      Performance Optimization with Enhanced RISC – Performance
Computing (POWER-PC)
PowerPC is a RISC architecture created by Apple–IBM–Motorola alliance, known as AIM. It was originally intended for personal computers design and is used in high performance processors.
8.      SuperH.
SuperH (SH) is a 32-bit reduced instruction set computer (RISC) instruction set developed by Hitachi.  It is implemented by microcontrollers and microprocessors for embedded systems.
Its major categories are SH1,SH2,SH3,SH4 and found applications in variety of applications.
9.      Scalable Processor Architecture (SPARC).
SPARC is a RISC instruction set architecture (ISA) developed by Sun Microsystems and introduced in 1986.
 

RISC v/s CISC : An Example

RISC VS CISC –  An Example of multiplication of two numbers in memory.
Suppose that the main memory is divided into locations numbered from (row) 1: (column) 1 to (row) 5: (column) 4. The execution unit is responsible for carrying out all computations. However, the execution unit can only operate on data that has been loaded into one of the four registers (A, B, C, or D). Let's say we want to find the product of two numbers - one stored in location 1:3 and another stored in location 4:2 and store back the result to 1:3
 A figure demonstrating an example of multiplication of two numbers in memory
Fig. 4: A Figure Demonstrating an Example of Multiplication of Two Numbers in Memory
 
CISC Approach

CISC design would try to finish the task in the minimum possible instructions by implementing hardware which could understand and execute series of operations. Thus the processor would come with a specific instruction ‘MUL’ in its instruction set. ‘MUL’ will loads the two values from the memory into separate registers, multiplies the operands in the execution unit, and then stores the product in the appropriate location. So, the entire task of multiplying two numbers can be completed with one instruction:

MUL 1:3, 4:2
MUL is referred to as a "complex instruction" as it operates directly on the computer's memory banks and does not require the programmer to explicitly call any loading or  storing functions.
 
RISC Approach

RISC processors use simple instructions that can be executed within a clock cycle. Thus, ‘MUL’ instruction will be divided into three instructions.

i)             "LOAD," which moves data from the memory bank to a register,
ii)             "PROD," which finds the product of two operands located within the registers, and
iii)            "STORE," which moves data from a register to the memory banks.
 
In order to perform the task, a programmer would need to code four lines of assembly:
LOAD A, 1:3
LOAD B, 4:2
PROD A, B
STORE 1:3, A
 
Analysis
1. RISC design uses more lines of code and hence, more RAM is needed to store the assembly level instructions. Also, the compiler must also perform more work to convert a high-level language statement into code of this form.

2. Since each instruction requires only one clock cycle to execute, the entire program will execute in approximately the same amount of time as the multi-cycle "MUL" command.

3. RISC "reduced instructions" require less transistors of hardware space than the complex instructions, leaving more room for general purpose registers.

4. As all of the instructions execute in a uniform amount of time (i.e. one clock), pipelining is possible.

5.  Separating the "LOAD" and "STORE" instructions actually reduces the amount of work that the computer must perform. After a CISC-style "MUL" command is executed, the processor automatically erases the registers. If one of the operands needs to be used for another computation, the processor must re-load the data from the memory bank into a register. In RISC, the operand will remain in the register until another value is loaded.
 

Comparison & Convergence

RISC VS CISC – Comparison
CISC
RISC
Emphasis on hardware
Emphasis on software
Includes multi-clock complex instructions
Single-clock, reduced instruction only
 
Memory-to-memory:
"LOAD" and "STORE" incorporated in
Instructions
Register to register:
"LOAD" and "STORE" are
independent instructions
Small code sizes, high cycles per second
Low cycles per second, large code
Sizes
Transistors used for storing complex
Instructions
Spends more transistors on memory registers
 
CISC and RISC Convergence
In the late 70s when computer revolution was gaining momentum, the hardware prices were quite expensive. RAM that had a capacity of few megabytes was worth thousands. CISC which is hardware emphasizing was the sole architecture and it made computing expensive and their repair even more. This was the main reason that IBM researched to develop RISC. The hardware prices have dramatically fallen since then and semiconductor processor technology has changed significantly since introduction of RISC chips in the early 80s. Because a number of advancements are used by both RISC and CISC processors, the demarcation between the two architectures is getting blurred. In fact, the two architectures almost seem to have adopted the strategies of the other. Because processor speeds have gone high, CISC chips are now able to execute more than one instruction within a single clock. This also allows CISC chips to make use of pipelining. With other technological improvements, it is now possible to fit many more transistors on a single chip. Similarly, RISC processors can make use of more complicated hardware incorporate more complicated, CISC-like commands.
 
Thus, we are on the verge of “post-RISC/CISC” era wherein two design approaches are converging. A new architecture named EPIC (Explicitly Parallel Instruction Computing) was launched at the beginning of the new millennium. It carried the pros of RISC as well as CISC.  EPIC based processor “Itanium” is commercially widely used by giants such as HP-Compaq and Unisys.
Present circumstances and heavy support from Intel have made CISC share the larger part of the smart computing market. However, RISC, due to its power efficient methods has made rapid progress in handheld and portable devices. Nintendo DS and Apple iPod are the most prominent examples for that. Thus both are strongly ahead to a long future unless a better design architecture gets evolved.

Comments

Does RISC mean anything like "It has less number of instruction set than CISC". And so why its is called as RISC....?

RISC has reduced number  instruction set although it requires a combination of many instructions to perform a task that would otherwise require one instruction in the CISC.

Also what does HAL and Semantic gap mean....?. Can you elobrate a liitle more about those two things....?

Thanks for the valuable information shared.

Last couple of lines are confusing.

CISC has less no.of instructions but each instruction a microcodes will be executed.Is that what you mean by large no.of instructions?

Very helpful study material..

What are a few instructions that aren't supported by RISC but are supported by CISC? Expand information as well if you don't mind. Thanks.

For example, if we were to multiply two numbers “a” and “b”, a simple complex instruction “MULT” would suffice for CISC but the same instruction would need more than one instruction in RISC since loading "a" and "b" into register would need to be explicit before performing the MULT instruction.

CISC

MULT 2:3, 5:2 ; where 2:3 = a, and 5:2 = b

RISC  

LOAD A, 2:3
LOAD B, 5:2
PROD A, B
STORE 2:3, A

 

Excelent article!
I've used it in a class and shared this link with the students.

Thank you!

Very nice ass
Wrong information Apple is the best. Intel sucks.

very nice and very cheap good work my friend

Why AVR is called as hybrid RISC and not RISC