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CISC & RISC Architecture

Written By: 

Preeti Jain


In layman terms, computers can be defined as a hierarchical series of metal, silicon and plastic (Hardware) fused with software all around it. These two entities combine to form a powerful machine that can process gigabytes of data in a span of a few seconds. The role played by hardware and software has always been closely studied so as to find which one should play the major part. Major Computer manufacturing firms Apple and Intel have always been arguing on importance of hardware and software in CPU architecture designs. Intel supporters want the hardware to bear more responsibility and software on the easier side. This would impact the hardware designing to be more complex but software coding would be relatively easy. On the other hand, Apple supporters want the hardware to be simple and easy and software to take the major role. Intel’s hardware oriented approach is termed as Complex Instruction Set Computer while that of Apple is Reduced Instruction Set Computer. Let’s have a thorough look on the basics, differences and pros and cons of these two well known CPU architecture designs.


Architecture of Central Processing Unit drives its working ability from the instruction set architecture upon which it is designed. Instruction Set Architecture can be defined as an interface to allow easy communication between the programmer and the hardware.  ISA prepares microprocessor to respond to all the user commands like execution of data, copying data, deleting it, editing it and several such and diverse operations. Some major terms that are often used in ISA are:
Instruction Set: It is a group of instructions that can be given to the computer. These instructions direct the computer in terms of data manipulation. A typical instruction consists of two parts: Opcode and Operand.
Opcode or operational code is the instruction applied. It can be loading data, storing data etc.
Oprand is the memory register or data upon which instruction is applied.
Addressing Modes: Addressing modes are the manner in the data is accessed. Depending upon the type of instruction applied, addressing modes are of various types such as direct mode where straight data is accessed or indirect mode where the location of the data is accessed.
Processors having identical ISA may be very different in organization. Processors with identical ISA and nearly identical organization are still not nearly identical.
CPU performance is given by the fundamental law:
cisc 1.JPG
Thus, CPU performance is dependent upon Instruction Count, CPI (Cycles per instruction) and Clock cycle time. And all three are affected by the instruction set architecture.
Instruction Count
Instruction Set Architecture
Physical Design
This underlines the importance of the instruction set architecture. There are two prevalent instruction set architectures:
Complex Instruction Set Architecture (CISC) : The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction.
Reduced Instruction Set Architecture (RISC): RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program
Subsequent sections will discuss RISC, CISC designs and their characteristics.
Both RISC and CISC architectures have been developed as an attempt to cover the semantic gap.
cisc 2.JPG
With an objective of improving efficiency of software development, several powerful programming languages have come up, viz., Ada, C, C++, Java, etc. They provide high level of abstraction, conciseness and power. By this evolution the semantic gap grows. To enable efficient compilation of high level language programs, CISC and RISC designs are the two options.
CISC designs involve very complex architectures including a large number of instructions and addressing modes, whereas RISC designs involve simplified instruction set and adapt it to the real requirements of user programs.



Does RISC mean anything like "It has less number of instruction set than CISC". And so why its is called as RISC....?

RISC has reduced number  instruction set although it requires a combination of many instructions to perform a task that would otherwise require one instruction in the CISC.

Also what does HAL and Semantic gap mean....?. Can you elobrate a liitle more about those two things....?

Thanks for the valuable information shared.

Last couple of lines are confusing.

CISC has less no.of instructions but each instruction a microcodes will be executed.Is that what you mean by large no.of instructions?

Very helpful study material..

What are a few instructions that aren't supported by RISC but are supported by CISC? Expand information as well if you don't mind. Thanks.

For example, if we were to multiply two numbers “a” and “b”, a simple complex instruction “MULT” would suffice for CISC but the same instruction would need more than one instruction in RISC since loading "a" and "b" into register would need to be explicit before performing the MULT instruction.


MULT 2:3, 5:2 ; where 2:3 = a, and 5:2 = b


LOAD A, 2:3
LOAD B, 5:2
STORE 2:3, A


Excelent article!
I've used it in a class and shared this link with the students.

Thank you!

Very nice ass
Wrong information Apple is the best. Intel sucks.

very nice and very cheap good work my friend


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