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CMOS (Complementary Metal-Oxide Semiconductor)

Table of Contents:

Written By: 

Preeti Jain

The first working point contact transistor developed by John Bardeen, Walter Brattain and William Shockley at Bell laboratories in 1947 initiated the rapid growth of the information technology industry. In 1958, J Kilby invented the first integrated circuit flip flop at Texas and soon after this; Frank Wanlass at Fairchild described the first CMOS logic gate (nMOS and pMOS) in 1963.

The most common description of the evolution of CMOS technology is known as Moore’s law. In 1963 Gordon Moore predicted that as a result of continuous miniaturization, transistor count would double every 18 months. The observation made by Gordon Moore was that the number of components on the most complex integrated circuit chip would double each year for the next 10 years. This doubling was based on a 50 – 60-component chip produced at that point of time compared with those produced in preceding years. Looks surprising, but his prediction has turned true and is being treated as a law.  The speed of transistors increases and their cost decreases as their size is reduced. The transistors manufactured today are 20 times faster and occupy less than 1% of the area of those built 20-30 years ago.  In 1971, Intel 4004 had transistors with minimum dimension of 10um and in 2003; Pentium 4 had transistors with minimum dimension of 130 nm. Having crossed 90nm, 65nm technological nodes, 32 nm and 22nm technology is in the pipeline. 53% compound annual growth rate is achieved over 45 years. No other technology has grown so fast so long. Transistors have become smaller, faster, consume less power, and are cheaper to manufacture.  It seems intuitively obvious that scaling cannot go on forever because transistors cannot be smaller than atoms.

The first integrated circuits hitting the markets in the seventies had a few 100 transistors integrated in bipolar technology.  Even though the principles were well known, MOS arrived in the markets several years later. One of the reasons behind this was the inherent instability of the MOS transistors due to the presence of minute amounts of alkali elements in the gate dielectric. This caused the threshold voltage of the transistor to shift during the operation.

However, soon the problems of high power consumption by bipolar circuits became dominant. Even in the case of all transistors being ‘OFF’, the sum of the leakage current in bipolar transistors is fairly large. To provide a solution for the problem of power consumption, MOS technology eventually made its way. Dimensions of MOS devices can be scaled down more easily than other transistor types.

In principle, MOS is better in terms of power consumption. MOS devices work with only switching voltages; current per se is not needed for the operation. MOS circuits do have lower power consumption; but they are also slower than their bipolar colleagues. Initially, NMOS got wider acceptance but with the increase in integration density, power consumption again became a problem. Afterwards, in eighties, CMOS processes were widely adopted. Present day chips would not exist if the CMOS technique would not have been implemented around the late eighties.


Silicon IC technologies can be primarily classified under three types:

{C·      Bipolar

Bipolar transistors have npn or pnp silicon structure. In these transistors, small current into very thin base layer controls large currents between emitter and collector. Base currents limit integration density of bipolar devices.


{C}·        Metal Oxide Semiconductor(MOS)

MOS is further classified under PMOS (P-type MOS), NMOS (N-type MOS) and CMOS (Complementary MOS). MOS derives its name from the basic physical structure of these devices; MOS devices comprise of a semiconductor, oxide and a metal gate. Nowadays, polySi is more widely used as gate. Voltage applied to the gate controls the current between source and drain. Since they consume very low power, MOS allows very high integration.


{C·        BiCMOS(Bipolar CMOS technology)

BiCMOS Technology utilizes both CMOS and Bipolar Junction transistors integrated on the same semiconductor chip.

CMOS offers high, symmetrical noise margins, high input and low output impedance, high packing density, and low power dissipation but speed is the only restricting factor. In contrast, the ECL gate has a high current drive per unit area, high switching speed, smaller propagation delay, but high power consumption makes very large scale integration difficult.

BiCMOS has made it possible to combine CMOS transistors and bipolar devices in a single process at a reasonable cost to achieve the high-density integration of MOS logic with the current-driving capabilities of bipolar transistors.


Some other variants of FETs have also come up, viz., Si-TFT, polySi-TFT, MESFET, etc. These are used for different applications.




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