AVR ATmega32 TWI Registers

AVR (ATmega32) contains some in-built registers for TWI communication which not only reduce the level of complexity but also make the whole communication process smooth.

These registers have been explained in this tutorial.

1. TWBR (TWI Bit Rate Register) :

TWBR7

TWBR6

TWBR5

TWBR4

TWBR3

TWBR2

TWBR1

TWBR0

This register is used in master mode to set the division factor for bit rate generator (SCL clock frequency). The bit rate generator unit controls the time period of SCL. The SCL clock frequency is decided by the Bit Rate Register (TWBR) and the prescaler bits of TWSR register (explained next).

2. TWSR (TWI Status Register) :

TWS7

—

TWPS1

TWPS0

· Bits7-3 – TWS: TWI Status

These bits reflect the status of TWI bus which will be explained later in the code explanation. The article focuses only those status conditions which will be used in the codes. For more details about rest of the status, please refer the data sheet.

· Bit 2- Reserved bit

· Bits1-0 – TWPS: TWI Prescaler Bits

These bits are used to set the prescaler of ‘Bit rate generator unit’.

TWPS1	TWPS0	Prescaler value
0	0	1
0	1	4
1	0	16
1	1	64

Value of Prescaler according to TWPS bits

Formula for SCL clock frequency :

Fig. 1: Image showing Formula for SCL Clock Frequency

3. TWDR (TWI Data Register) :

TWD7

TWD6

TWD5

TWD4

TWD3

TWD2

TWD1

TWD0

TWDR always contains the last data present on SDA bus. In transmitter mode the TWDR contains the next byte to be transmitted. While in receiving mode the TWDR contains the last byte received. The data in TWDR remains stable as long as TWINT flag is high.

Continued

4. TWCR (TWI Control Register) :

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

—

TWIE

· Bit 7 – TWINT: TWI interrupt flag

This bit is used to monitor the current status of the TWI. TWINT is set by hardware when TWI has finished its current job. SCL will be low till the time TWINT bit is set. TWINT flag must be cleared by software before starting any operation on TWI.

Note: TWINT flag is cleared by writing a logic one to it.

· Bit 6 – TWEA: TWI Enable Acknowledge Bit

The TWEA bit is use to generate the acknowledgement pulse. If the TWEA bit is written to one the ACK pulse is generated. And on the other hand if TWEA bit is zero, the device can be virtually disconnected from the two wire serial bus temporarily.

Note: The TWI status values are different when data is transferred on the basis of receive the ACK (TWEA is set) or the NOT ACK (TWEA is clear) pulse.

· Bit 5 – TWSTA: TWI START Condition Bit

By writing one to this bit the device becomes master controller. It check if the bus is available (bus is not busy in transmission for other masters) and then generates the start condition on the bus. If the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim for being the master of the bus.

· Bit 4 – TWSTO: TWI STOP Condition Bit

By writing one on TWSTO bit, the master will generate a STOP condition on Two Wire Serial Bus. When STOP condition is executed on the bus, the TWSTO bit is cleared automatically.

· Bit 3 – TWWC: TWI Write Collision Flag

This bit is used to avoid the collision in writing to TWDR. The TWWC bit will get set when TWDR is attempting to write (TWINT flag is low). The TWWC flag is cleared by writing TWDR when TWINT is high.

· Bit 2 – TWEN: TWI Enable Bit

The TWEN bit is use to enable/disable the TWI interface. When this bit is written to one, the TWI operation is enabled. If this bit is written to zero, the TWI is switched off and the TWI transmission gets terminated.

· Bit 1 – Reserved Bit and always written as zero.

· Bit 0 – TWIE: TWI Interrupt Enable

The TWIE bit is use to enable/disable the TWI interrupt request. Interrupt request get enable by writing one to it and disabled by writing zero to it.

5. TWAR (TWI (slave) Address Register) :

TWA6

TWA5

TWA4

TWA3

TWA2

TWA1

TWA0

TWGCE

· Bits 7-1 – TWA: TWI(slave) Address Bits

These bits are use to store 7-bit slave address to which TWI responds when programmed as Slave Transmitter or Receiver.

· Bit 0 – TWGCA: TWI General call Recognition Enable Bit

This bit is used to enable the slave to acknowledge for the general call address (0x00).

The general call addresses all devices on the bus using the I²C address 0.

If a device does not need the information provided, it simply does nothing. Devices processing the message acknowledge this address and behave as slave receiver.

The master cannot detect how many devices are using the message. The second byte contains a command.

Also see TWI interfacing with ATmega32