Diodes Incorporated recently introduced the PI7C9X3G808GP, a PCIe 3.0 packet switch that’s capable of delivering the elevated performance parameters mandated by modern data center, cloud computing, network-attached storage (NAS), and telecom infrastructure implementations.
This new packet switch supports 8-lane operation, accommodating 2, 3, 4, 5, and 8-port configurations. Cut-through, store, and forward modes can all be used with a packet-forwarding latency of less than 150ns (typical).
The proprietary architecture employed in the PI7C9X3G808GP packet switch provides enhanced flexibility and performance. Multiple port/lane width combinations are available, as well as cross-domain, end-point (CDEP) arrangements. Thanks to its CDEP capabilities, the PI7C9X3G808GP supports fan-out and dual-host connectivity.
The built-in PCIe 3.0 clock buffer allows for a reduction in the overall component count and helps to curb BOM costs. This integrated buffer is unique to the industry because of its low-power operation. Three different reference clock options can be used: common, separate reference no spread (SRNS), and separate reference independent spread (SRIS).
Multiple direct memory access (DMA) channels have also been embedded into the switch, so as to make communication between host (or hosts) and connected end-points as efficient as possible.
Features include error-handling, advanced error reporting, and end-to-end data protection with error correction and key functionality in terms of reliability, availability, and serviceability (RAS). Advanced power management means the switch is aligned with the most stringent energy-saving requirements.
The hot-pluggable ports that are empty are kept in a low-power state until they are needed. While under full-load conditions and 80° C junction temperature, the PI7C9X3G808GP will draw only 2.9W of power. Diodes’ PI7C9X3G808GP is supplied in a high-performance, flip-chip package, with 196-ball BGA format. It has dimensions of 15 x 15mm.
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