Field Programmable Gate Arrays (FPGA)
Some of you may be familiar with the terms FPGA or Field Programmable Gate Array. And familiarity does not necessarily beget understanding. So what exactly is FPGA?
In simple terms it is a logic chip which contains a two dimensional array of logic cells and programmable switches. They are ICs that contain an array of identical logic blocks with programmable interconnections.Just as on a blank canvas you can paint any picture you want, FPGA allows an engineer to design any digital circuit. They say: just generate the bit file, download it and you’re good to go! This is a big development over the traditional microcontrollers as the architecture of such controllers does not support larger designs. For example, microcontrollers like 8051 used Harvard architecture with CISC instruction set. FPGA does not have any inbuilt instruction sets which provide the designer with much greater flexibility. A controller has its own CPU which starts the controller, retains memory and performs several tasks. Unlike microcontrollers, a FPGA will not be able to start functioning on itsown due to lack of the traditional architecture.
Fig. 1: Representational Image of a Typical FPGA Device
If you compare it with a microcontroller, FPGA has many benefits. It is much more flexible as it allows you to design any design desired whereas a controller has limited functionality. It also offers higher memory availability. The main difference between the two is that a FPGA can control hardware whereas a microcontroller can control software. This is why FPGA is normally programmed in Hardware Descriptive Languages (HDLs).
Other technologies that have a concept similar to that of FPGA are Application Specific Integrated Circuit (ASIC) and Complex Programmable Logic Device (CPLD). They differ in terms of applications, number of gates and basic architecture. ASIC stands for Application Specific Integrated Circuit. As the name suggests, it is designed for a particular application whereas FPGA gives the freedom to execute any design. FPGA also has the ability to reprogram in case of bugs whereas ASIC cannot be reprogrammed. These are also programmed by HDLs. The advantage of ASIC over FPGA is that FPGAs run slower than ASICs. However, FPGAs can be made to act like ASICs which gives them an added benefit.
The next comparison is that of FPGA and CPLD (Complex Programmable Logic Device). CPLD consist of characteristics of PAL (Programmable Logic Array) as well as FPGA.Main comparison points include:
1. CPLDs have non-volatile memory whereas FPGAs have volatile memory. This means that upon Power-ON, a CPLD holds memory whereas a FPGA erases the previous data. This is why a FPGA requires an external ROM. This memory is given to the FPGA upon power ON so that previous data is restored.
2. The main element of a CPLD is a macrocell. A single macrocell consists of several AND gates, a D flip-flop, a multiplexer and an EX-OR gate. They are connected using a block called programmable interconnect. The main element of a FPGA is a Look-Up Table (LUT).In a Xilinx device, a LUT is basically a function generator which can also provide a 16×1 bit synchronous RAM as well as a ROM. Function generators are implemented as 4 input LUTs.
3. Also, the number of gates available in CPLD is less as compared to FPGA. A CPLD has approximately 500 to 12,000 gates whereas a FPGA has 3,000 to 5,00,000 gates.
4. Cost of a FPGA is higher than that of CPLD.
So, a FPGA is selected as it is flexible and has more number of gates. These points matter when it comes to designing complex circuits. As a FPGA can be programmed to function as an ASIC, it is preferred over the others.
ARCHITECTURE OF FPGA:
As the figure shows, the main blocks of any architecture are Configurable Logic Blocks (CLBs) or Logic Blocks, interconnect and I/O lines.
Fig. 2: Graphical Image Showing FPGA Architecture
A CLB can be called the basic building block of a FPGA. It is basically a logic cell which can be configured or programmed to perform required functions. These are connected to the interconnect block. A CLB can be implemented using either LUT based logic or Multiplexer based logic. In LUT based logic, the block consists of look up table, a D Flip-flop and a 2:1 Multiplexer. Flip Flops are used as storage elements. The Multiplexer selects the appropriate output.
Each CLB is made up of certain number of slices. Slices are grouped in pairs and arranged in columns. The number of CLBs in a device varies according to the vendor and the family of the device. For example, the Xilinx make Spartan 3E FPGA contains four slices. Each slice is made up of two LUTs and two storage elements. The function of LUT is to implement logic whereas the dedicated storage elements can be flip-flops or latches. The CLBs are arranged in an array of rows and columns.
Fig. 3: Diagrammatical Image of FPGA Building Block – LUT Based CLB
Fig. 4: Graphical Presentation of MUX Based CLB – FPGA Building Block
Fig. 5: Figure Explaining Arrangement of CLBs in Spartan3E FPGA
Interconnect is the programmable network of signal pathways. These exist between inputs and outputs of functional elements within the device. This is also known as routing. Types of routing include local routing for interconnection between LUTs, Flip-flops and general routing matrix, general purpose routing for interconnection between the rows and columns of CLBs, I/O routing for the purpose of pin-swapping or locking. This is done for the purpose of adaption of new designs to the existing PCB layout.Other routing methods include dedicated routing sources improve performance, global routing distributes clock and other signals.
Fig. 6: Cross-Sectional Diagram of Direct Interconnect Technique Used in FPGA Devices
Input/ Output Blocks (IOBs) offer programmable unidirectional or bidirectional interface between the package pins and the device’s internal logic. There are three signals present within an IOB: input path to carry data from the pad to the respective line, output path carries data from the internal logic to the IOB pad via a multiplexer and a three state driver. The last signal is the three state path which determines the state of high impedance of the output driver. All the signals come with an option of an inverter.
A Spartan2 FPGA Input/Output Block
Fig. 7: Block Diagram Showing Sparatan2 FPGA Input/Output Details
Distributed and Block RAM
The concept of distributed and block RAM exists mainly in Xilinx devices. Most of the CLBs of a Xilinx device contain a small RAM which maybe single port or double port. As this RAM is spread throughout the FPGA over several LUTs, it is called distributed RAM. The disadvantage of distributed RAM is that it cannot be used for larger designs as a single CLB is not enough. You can implement several block RAMs in parallel in order to implement larger and wider memory. The Xilinx synthesizer tool infers which memory is to be used with the help of your code. A large sized RAM can be generated by using a parallel array of large number of elements.
Block memory is a dedicated block of two port memory. It consists of several kilobytes of RAM . The number of block RAMs present in the FPGA depends on how advanced the FPGA is. For example, Spartan 6 FPGA has a larger sized block RAM than Spartan 3. Block RAM should be used for large sized implementations.
The two memories have different modes of operation. While the WRITE operation is synchronous for both, the READ operation varies. For distributed RAM, data is read directly as soon as it is entered. It does not wait for the clock signal. This means it is asynchronous. On the other hand, block RAM operates on synchronous mode of operation. This means that data can be written into the memory only at the rising edge of the clock.
The implementation style can be forced to implement either of the two RAMs by using ram_style constraint.
Programming a FPGA
There are two languages which can be used to program a FPGA: VHDL, Verilog and System Verilog.
VHDL stands for Very High speed integrated circuit Hardware Descriptive Language. It has all the features real life hardware possesses.
The key features of this language include the following:
1. It is a concurrent language. This implies that statements can be implemented in a parallel manner similar to real life hardware.
2. It is a sequential language which means statements are implemented one after another in a sequence.
3. It is a timing specific language. This means that the signals like clocks can be manipulated as per your requirement. For example, you can start a process only when the clock is on rising edge, provide adequate delay, invert the clock, etc.
4. It is not case sensitive. VHDL code is translated into wires and gates which are mapped onto the device.
The different modelling styles of VHDL include behavioural, structural, dataflow and a combination of all three. Combinational and sequential statements may be used to implement the modelling styles. Sequential statements are implemented one after another (Serially). On the other hand, combinational statements are executed simultaneously (in a parallel manner).
In behavioural style, just the functions are described. It is implemented mainly using the PROCESS statement. The architecture of registers is not defined.
In structural type, the circuit is described in terms of interconnected components. For example, a full adder implemented in terms of two half adders..
In dataflow style, circuit is described using concurrent statements. For example, a MUX may be described in terms of gates such as EXOR (in other words implemented as per the Boolean expression obtained from the truth table). This is not a very realistic way of writing a code as it has several dependencies and has use concurrent statements.
Mixed modelling style can use any combination of all three styles mentioned above.
The following code is a behavioural implementation of a 4 bit counter in VHDL.
entity counter is
Port ( clk : in STD_LOGIC;
out_count : out STD_LOGIC_VECTOR (3 downto 0));
architecture Behavioral of counter is
variable count:std_logic_vector(3 downto 0):=”0000″;
if(clk’event and clk=’1′) then
Fig. 8: The RTL Schematic
Verilog is also a Hardware Descriptive Language which is mostly used to design and verify digital circuits and RTL level of abstraction. It allows designs at various levels of abstraction. It has C like syntax.
Fig. 9: Example Showing How Verilog Defines Hardware in FPGA Devices
Verilog has three levels of abstraction: behavioural, RTL and gate level.
In behavioural abstraction, a system is described by a concurrent algorithm. In RTL, a system is implemented by transferring data between registers with respect to a clock. In gate level of abstraction, a system is characterized by timing and logical links.
A Verilog system is built by modules and ports. A Verilog system is made of modules which are made up of various components. A module may consist of instances of other modules. A port may be of three types: input, output, inout.
1. Parameters: constants whose value is specified at time of compilation.
2. Nets: used to connect components together
3. Registers: these are storage elements. Values are stored during procedural statements. Types of registers are reg, integer, type and real.
4. Primitives and Instances: predefined module types like the logical gates.
5. Continuous Assignments: these describe how data moves from one place to another (from a net or a register).
6. Procedural Blocks: These represent sequential behaviour. These are sequences of executable statements.
7. Task/Function definitions: implemented only within the procedural block.
Fig.10: Block Diagram Showcasing Heirarchy of Verilog System
VHDL v/s VERILOG
Both these languages are equally effective when it comes to hardware description. The choice depends on factors like personal choice, EDA tool availability and commercial, business and marketing issues.
In terms of compilation, in VHDL, compilation of multiple design units residing in the same file differently is possible. In verilog, compilation is a way of speeding up simulation.
In terms of data types, VHDL offers a wide choice of data types (user defined and otherwise). In Verilog, all data types are pre-defined. Despite this drawback, Verilog data types are easy to use and are focused on the modelling aspect of hardware instead of the abstract aspect. For high level constructs, VHDL is preferred whereas Verilog is preferred because of its simplicity. VHDL offers various libraries, Verilog does not.
VHDL helps managing large designs with the help of configuration, generate generic and package. Verilog has no statements all help manage large design structures. As Verilog exhibits C-like features, it is easier for beginners to pick up as compared to VHDL.
APPLICATIONS OF FPGA
Due to its advantages, FPGA is suitable for a wide range of industries ranging from aerospace and defence to automobiles. This is mainly because FPGA is customizable. Companies like Cisco use FPGA in their switches and routers so as to increase speed of the hardware.
In audio, FPGA is used in portable electronics, digital signal processing, etc. In radio astronomy, FPGA gives better performance in terms of computation as compared to that of a microprocessor and a DSP.
FPGAs also find potential use in nuclear power plant operators. This is because FPGA-based systems can be made simpler, more testable, less reliant on complex software and easier to qualify for safety and safety-related application. FPGA-based systems have now started to sappear in new plant I&C designs, as well as in replacements and upgrades for operating plants.
In the medical field, FPGAs are used in CT scanners, MRI machines, ultrasound machines, X-ray machines and surgical systems.
Along with these applications, FPGAs can also be found in wireless communication systems, security systems, in automotive applications, in scientific instruments and in high performance computing.
Hence, due to flexibility, customization and low cost, FPGAs are of use in various fields.
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