**By Krupa Bhavsar****, Applications Engineer, Dialog Semiconductor**

Sine waves are continuous waves, which describe a smooth periodic oscillation. These waves are generally used in signal processing and engineering fields.

In this article, dual sine waves with the opposite polarity shown in Figure 1 are generated without coarse PWM “steps”. For generating sine waves, two PWM macrocells are used. One PWM macrocell with pre-programmed frequencies generated through a register file is configured as a frequency-controlled generator. This frequency-controlled generator then modifies the duty cycle of another PWM macrocell.

This project is divided into three sections. The Clock Frequency Generation section describes calculations to generate new clock frequencies for a PWM macrocell based on the input frequency and desired sine wave frequency. In the HV PAK section, the circuit design is showed and explained. Finally, the Test Setup and Future Expansion section provide additional details on testing conditions and other possibilities that this project has.

**Clock frequency generation**

The new clock frequency generation depends upon the input frequency and sine wave frequency. The number of PWM periods required for a specific sine wave is the ratio of input frequency and frequency of the sine wave.

Equation 1

The sine wave is divided into 4 quarters, and the number of clocks after which the PWM direction changes is calculated based on the number of PWM periods and total quarters of a sine wave, i.e., 4.

Equation 2

16-byte register file generates 16 different clocks for the PWM macrocell. The equation below (3) shows when a new clock inside the PWM macrocell should be generated per quarter of the sine wave. This New Clock Frequency is the frequency at which the next PWM duty cycle is generated.

Equation 3

This project used the GreenPAK™ circuit to illustrate how the sine wave generator can be built – specifically SLG47105 High Voltage GreenPAK (HVPAK). The complete circuit design file created in the GreenPAK Designer software (available for free) can be found here.

Figure 2 shows the design. This design requires only one external input, i.e., Sleep input. In this design, the PWM1 macrocell is configured as a frequency-controlled generator which generates a new clock frequency for each quarter of the sine wave and updates the duty cycle of the PWM0 macrocell. The output of the PWM0 macrocell is connected to HV OUT CTRL0, which is then connected to the external filters to obtain dual sine waves with reverse polarity.

In this project, the HVPAK design is configured to generate a 200Hz sine wave using a 100kHz input frequency.

In this design, the PWM1 macrocell is configured to generate 100kHz input frequency. The PWM output generates dual sine waves with inverse polarity using HV OUT CTRL0 macrocell as long as Sleep input is LOW. If Sleep input is HIGH, then PWM macrocells are OFF, and HV (High-Voltage) outputs of HV OUT CTRL0 macrocell are Hi-Z. PWM1 macrocell is configured to generate 16 different clocks for each quarter of the sine wave using its 16-byte register file. 500 periods per sine wave are required to generate a 200Hz sine wave using a 100kHz input signal.

As we can see in equation #1, 500 periods per sine wave are required to generate a 200Hz sine wave using 100kHz input signal.

The direction of PWM changes every 125 clock periods (Equation 2). CNT1/DLY1 counts ~125 clock periods of the input 100kHz signal. DFF6 is configured as a toggle flip-flop which changes the direction of both PWM macrocells ~125 counts.

As shown in equation #3, a new clock frequency should be generated ~8 PWM periods, so the Duty Cycle Clock property of the PWM1 macrocell is selected to be Period CNT ovf/8.

The PWM1 macrocell’s output is fine-tuned using OSC and connected to the PWM0 macrocell’s Duty cycle clock input. The output of the PWM0 macrocell is the desired PWM output which is used to generate sine waves of opposite polarity using the HV OUT CTRL0 block.

The HV OUT CTRL0 macrocell is configured in Full Bridge mode with PH-EN mode control configuration. The PWM0 output is connected to PH input, and EN input is connected to DDF3 to change the polarity of the sine wave every half cycle. Two pairs of external filters are required to generate dual sine waves from the PWM output.

So, to generate a sine wave of the desired frequency using the desired input frequency, the designer first calculates the necessary parameters to modify PWM macrocells as described in the Clock Frequency Generation section and then modify the PWM macrocell and CNT settings accordingly as described above.

**Test**** setup and future expansion**

This design is tested using two external resistors and capacitors and a push-button. The push-button is connected to the Sleep input, and each resistor and capacitor pair is connected to the HV output of the HV OUT CTRL0 macrocell, as shown in Figure 3. As shown in Figure 4, dual sine wave approximations with opposite polarity are generated when Sleep input is LOW.

Channel 1 (yellow/top line) – Pin #2 (Sleep)

Channel 2 (green/2nd line) – Sine wave output at Pin #7 (Out1)

Channel 3 (blue/3rd line) – Sine wave output at Pin #8 (Out2)

Future possibilities of this design can be expanded to generate sine waves through an I2C enabled MCU instead of a push button and include protection features such as constant current/current limit using Current Sense Comparator and Under-Voltage lockout (UVLO). This design can also be expanded to generate additional dual sine waves using HV OUT CTRL 1 macrocell.

**Conclusion**

The HVPAK design described in this article generates two 200Hz sine wave approximations with 100kHz input frequency. The design is easy to use, minimizes cost, saves board space and component count.

Moreover, the circuit that we used is quite flexible, easy to test, and can accommodate last-minute design changes. Once the design is modified, a new design file can be programmed on-chip and re-soldered on board. Using this design, the user can generate sine waves of desired frequency using PWM macrocells and a single input. It also offers design security by locking the design file to limit visibility.

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