This article explores the implementation of a voltmeter using the AnalogPAK SLG47011, featuring a 3-digit, 7-segment dynamic display. The design leverages the device’s ADC with a programmable gain amplifier (PGA) for voltage measurement, while the Memory Table and Width Converter enable dynamic visualization on the display.
Depending on the switch position, the voltmeter operates in two selectable voltage ranges — from 9.99 to 99.9 V. The configurable nature of the SLG47011 allows for adjustments to the voltage range by modifying the resistive divider and updating the Memory Table.
A dynamic display technique is employed, where individual digits of the 7-segment display are activated in sequence. The rapid switching creates the perception of a continuously illuminated 3-digit readout.
Operating principle and design
Figure 1 shows the circuit schematic of the voltmeter with a 3-digit, 7-segment display.
Figure 1. The circuit schematic of the voltmeter design with a 3-digit, 7-segment indicator.
The VIN voltage is applied to PIN 7 through a resistive divider 62 kΩ / 728 kΩ (666 kΩ + 62 kΩ) and 12 kΩ depending on the position of switch SW1. SW1 also affects the maximum allowable voltage (Vmeasured) and decimal point (DP) position.
PIN 8 activates the 1st digit and decimal point. PIN 6 activates the 2nd digit and decimal point. PIN 4 activates the 3rd digit.
The signal from PIN 7 then goes to the single-ended input of the PGA (buffer mode, mode #6) and then to ADC CH0 for further sampling. The maximum allowable voltage before the resistive divider, Vmeasured, is 9.99 V when the resistance of 62 kΩ is selected, and 99.9 V when 728 kΩ is selected.
The maximum voltage after the resistive divider is calculated by the following formulas:
The ADC converts this voltage to a 10-bit code using the formula below.
So, the maximum value of VINdec is 1024. The GreenPAK design file, we created in the Go Configure Software Hub, is shown in Figure 2.
Figure 2. The GreenPAK Design for the voltmeter with the 3-digit, 7-segment indicator.
SLG47011 includes a Memory Table macrocell that can hold 4096 12-bit words. This space is enough to store the value of each of the three indicator digits for each VINdec – 1024 x 3 = 3072 values in total. In other words, the “3n” word of the Memory Table corresponds to the 1st digit, the “3n + 1” word corresponds to the 2nd digit, and the “3n + 2” word corresponds to the 3rd digit of the corresponding Vmeasured. Where n = VINdec.
The ADC output value arrives at the MathCore macrocell, where it’s multiplied by three. Then this value is used as an address in the Memory Table. Assuming the ADC output is 1000, the MathCore output will be 3000. This means the Memory Table values at 3000, 3001, and 3002 addresses will be used and correspond to the indicator’s 1st, 2nd, and 3rd digits, accordingly.
Data from the MathCore output goes to the IN+ CH0 input of the Multichannel DCMP macrocell. This data is compared with data on the IN- CH0 input, which is taken from the Data Buffer0 output. Data Buffer0 stores the data from the CNT11/DLY11/FSM0 macrocell, which operates in Counter/FSM mode.
The Counter/FSM is reset to 1 when the HIGH signal from the ADC Data ready output arrives and starts counting upward. The Multichannel DCMP OUT0 output is connected to the Keep input of CNT11/DLY11/FSM0. This means that when CNT11/DLY11/FSM0’s current value is equal to the MathCore output value, the DCMP OUT0 is HIGH, and the Keep input of the CNT11/DLY11/FSM0 is also HIGH, keeping the counted value for further addressing to the Memory Table.
At the same time, together with CNT11/DLY11/FSM0, the Memory Control Counter is counting upward from 0. It sends the necessary address to the Memory Table.
Therefore, when the ADC measures a certain voltage value, the described comparison will point to the corresponding voltage value stored in the Memory Table – 3 consecutively recorded digits, which will dynamically be displayed on the 7-segment display.
The stored data in the Memory Table goes to the Width Converter macrocell, which converts the serial 12-bit input into the parallel 12-bit output.
The 3-bit LUT5 enables the decimal point (DP) through PIN 16 based on the states of PIN 3 (SW1.2), 2-bit LUT1 (1st digit), and 3-bit LUT0 (2nd digit).
Since the dynamic display method is used in this design, the digits will be ON sequentially with a period of 300 μs. This period is set by the CNT2/DLY2 (Reset Counter Mode) macrocell. 3-bit LUT4 sets the clock to the Width Converter based on synchronization with the CNT11/DLY11/FSM0 clock and the DCMP OUT0 state.
The P DLY, DFF8, and 3-bit LUT12 macrocells form a state counter for the Up/Down input of the Memory Control Counter macrocell based on the state of digit 2 (falling edge of the Width Converter OUT2).
When the first digit is ON, the Memory Control Counter counts upward by 1; when the 2nd digit is initially set ON, the state counter is set to LOW, forcing the Memory Control Counter count down, but it has already activated the 3rd digit. Therefore, the 2nd digit is activated again, and the state counter goes HIGH, forcing the Memory Control Counter to count upward, but it has already activated the first digit. Thus, all three digits will be sequentially activated until the new measured value from the ADC microcell is available.
CNT8/DLY8, CNT12/DLY12/FSM1, and 3-bit LUT7 are used to correctly turn on the ADC after the first turn-on when the POR signal arrives, as well as in further operations when turning the ADC off and on. CNT12/DLY12/FSM1 provides a period of 1.68 s, so the voltmeter value is updated every 1.68 s.
The Memory Table filing-in algorithm
The algorithm below is shown for a voltage of 9.99 V and a resistive divider of 62 kΩ and 12 kΩ. Since the second mode uses ten times the voltage and a ten times larger resistive divider, the memory table values will be similar; only the decimal point placement in the design is changed.
For each VINdec value, three values are assigned in the memory table: each VINdec corresponds to three consecutive values in the memory table 3n, 3n + 1, and 3n + 2, where n = VINdec.
Three columns for 3n, 3n + 1, and 3n + 2 should be created. They correspond to the indicator’s 1st, 2nd, and 3rd digits, respectively. The first column is assigned to the first digit of the rounded Vmeasured value. The second column is assigned to the second digit, and the third column is assigned to the third digit.
For each column’s digit, a 7-bit binary value is found (m11 – m5), corresponding to the activation of the corresponding digit of the seven-segment display (Table 3).
The next step is to add 5 more bits (m4-m0) to this value to the right to get a 12-bit number.
In the case of a design where a decimal point is only needed after the first or second digit, the 8th bit (m4) “decimal point” value can be written, and the corresponding Width Converter output, which is connected to PIN 16. Since decimal point logic is currently activated using the logic based on the states of the 1st and the 2nd digits and the switch (PIN 3), this bit can be written 0 or 1 without any difference, since it is not connected.
The 9th bit (m3) is responsible for turning on the first digit, the 10th bit (m2) is responsible for turning on the second digit, and the 11th bit (m1) for the 3rd digit. Since a 7-segment indicator with a common cathode is used, turning on the digit is done with a LOW level (0). Therefore, for the first column with words of type 3n, the 9th bit (m3) will equal ‘0’, while the 10th (m2) and the 11th (m1) bits will equal ‘1.’
For the second column with words of type 3n+1, the 10th bit (m2) will be equal to ‘0,’ while bits 9th (m3) and 11th (m1) will be equal to ‘1’. For the third column with words of type 3n+2, the 11th (m1) will be equal to ‘0’, while bit 9 (m3) and bit 10 (m2) will be equal to ‘1.’
The 12th bit (m0) is not connected, so its value does not affect the design.
The resulting 3072 binary 12-bit values must be converted to hex.
The required values for the Memory Table are already determined; now, they need to be sorted in ascending order of the Word index and inserted into the appropriate location in the software. For a better understanding of the connections between the Memory Table and the Width Converter, see Figure 3.
The testing results
Figure 4 shows the result of measuring 7.77 V in 62 kΩ mode with 12 kΩ resistive divider (up to 9.99 V). The decimal point is active after the first digit.
Figure 4. The voltage range up to 9.99 V: 7.77 V.
Figure 5 shows the result of measuring the same 7.77 V, but in 728 kΩ mode with 12 kΩ resistive divider (up to 99.9 V). The decimal point is now active after the second digit.
Figure 5. The voltage range up to 99.9 V: 7.7 V.
Figure 6 shows the result of measuring 17.0 V in 728 kΩ mode with 12 kΩ resistive divider (up to 99.9 V). The decimal point is active after the second digit.
Figure 6. The voltage range up to 99.9 V: 17.0 V.
Conclusion
This article provides a step-by-step overview of designing a voltmeter with a 3-digit, 7-segment display. Depending on the circuit configuration, the voltmeter operates in two selectable voltage ranges – 9.99 V and 99.9 V.
Voltage measurement is performed using the ADC with a programmable gain amplifier (PGA), while the Memory Table and Width Converter enable dynamic visualization on the display. The design’s flexibility allows for adjustments to the voltage range by modifying the resistive divider and updating the Memory Table, making it adaptable to different measurement needs.
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