In the previous tutorial, it was discussed how arithmetic operations on binary numbers can be implemented by the means of boolean logic operations. In a digital circuit, the logic operations are executed by logic gates. A Logic gate is an electronic circuit which makes logical decisions. The AND, OR and NOT are the basic logic gates.

The NAND and NOR gates are derived from these. Any computing problem in digital circuitry can be expressed by a boolean equation or boolean expression. A boolean expression can be minimized to Minterms or Maxterms reducing the expression to a two-level implementation which can be designed with the NAND or NOR gates. That is why, NAND and NOR gates are called the Universal gates. The exclusive â€“ OR gates is another logic gate which can be constructed using basic gates such as OR and NOT gates.

The logic gates can have two or more inputs and only one output expect for the NOT gate, which has only one input. The output signal from a logic gate appears only for certain combinations of the input signals as the number of combinations is always limited by the number of boolean variables (where each boolean variable represent an input channel).

So, basically, the logic gates are the building blocks of a digital circuit that can perform basic manipulation of the binary information. Any digital IC contains nothing but interconnected network of logic gates. Each gate is represented by a distinct logic symbol and its operation can be described by means of an algebraic function. The relationship between the input and output variables of each gate can be represented by means of a truth table and signal response of any logic gate can be represented by the timing diagram. So, let us learn about various logic gates.

**OR Gate** –

The OR gate performs logical addition, commonly known as OR function. The OR gate has two or more inputs and only one output. The operation of OR gate is such that HIGH (1) on the output is produced when any of the inputs is HIGH (1). The output is LOW (0) only when all the inputs are LOW (0). Suppose, if A and B are the input variables of an OR gate and Y is its output, then

*Y = A + B *

Similarly, for more than two input variables, the output of OR gate can be expressed as follow –

Y = A + B + C + D +â€¦â€¦

An OR gate built using diodes is shown below in which A and B represent the inputs and Y the output. The resistance **RL **is the load resistance. The Logical symbol of OR gate is also shown below –

*Fig. 1: OR Gate Symbol A**nd Circuit*

If A = 0 and B = 0, both the diodes will not conduct, hence the output Y = 0. If A = 1 and B = 0, diode D1 conducts, hence the output Y = 1. If A = 0 and B = 1, diode D2 conducts, hence the output Y = 1. If A = 1 and B = 1, both the diodes conduct and hence Y = 1. The output of an OR gate for two boolean variables can be represented by the following truth table –

The truth table for OR gate can be graphically represented by the following timing diagram –

*Fig. 2: OR Gate Timing Diagram*

**AND Gate** –

The AND gate performs logical multiplication, commonly known as AND function. The AND gate has two or more inputs and a single output. The operation of AND gate is such that the HIGH (1) is only when all the inputs are HIGH (1). Even when one of the inputs is 0, the output will be zero. Suppose, if A and B are the input variable of the AND gate and Y is its output, then

*Y = A **Â·** B *

The dot (Â·) denotes the AND operation, but typically it can also be written as Y = AB. The two input AND gate built using the diodes is shown below in which A and B represent the inputs and Y the output. The Logical symbol of AND gate is also shown below –

*Fig. 3: AND Gate Symbol And Circuit*

If A = 0 and B = 0, both the diodes conduct as they are forward biased, hence the output Y = 0. If A = 0 and B = 1, the Diode D1 conducts as they are forward biased, and hence the output Y = 0. If A = 1 and B = 0 the diode D2 conducts as they are forward biased, and hence the output Y = 0. If A = 1 and B = 1 both the diodes donâ€™t conduct as they are reverse biased, and hence the output Y = 1. The output of an AND gate for two boolean variables can be represented by the following truth table –

The truth table for AND gate can be graphically represented by the following timing diagram –

*Fig. 4: AND Gate Timing Diagram*

**NOT Gate** –

The NOT gate performs the basic logical function called Inversion or the complementation. The purpose of this gate is to convert the one logic level into the opposite logic level. It has one input and one output. When the High level is applied at the input the low level appears at the output and vice-versa. A NOT gate built using a transistor is shown below, where A represent the input and Y represents the output. The Logical symbol of NOT gate is also shown below –

*Fig. 5: Gate Symbol And Circuit*

When the input is HIGH, the transistor is in the ON state and the output is LOW. When the input is LOW, the transistor is in the OFF state and the output is HIGH. The output of a NOT gate can be represented by the following truth table –

The truth table for NOT gate can be graphically represented by the following timing diagram –

*Fig. 6: NOT Gate Timing Diagram*

**NAND Gate** –

The NAND gate performs the logical function which is the serial combination of the NOT and AND Gates. It has two or more inputs and only one output. The Logical symbol for the NAND gate is shown below –

*Fig. 7: NAND Gate Symbol*

At a NAND gate, when all the inputs are HIGH, the output is LOW. When any one of the inputs is LOW, then the output is HIGH. The output of a NAND gate for two boolean variables can be represented by the following truth table –

The truth table for NAND gate can be graphically represented by the following timing diagram –

*Fig. 8: NAND Gate Timing Diagram*

**NOR Gate** –

The NOR gate performs the logical function which is the serial combination of the NOT and OR Gates. It has two or more inputs and only one output. The Logical symbol for the NOR gate is shown below –

*Fig. 9: NOR Gate Symbol*

At a NOR gate, when all the inputs are LOW, the output is HIGH. When any one or both of the inputs is HIGH, then the output is LOW. The output of a NOR gate for two boolean variables can be represented by the following truth table –

The truth table for NOR gate can be graphically represented by the following timing diagram –

*Fig. 10: NOR Gate Timing Diagram*

**EXCLUSIVE â€“ OR (****Ex â€“ OR****) Gate** –

An Exclusive â€“ OR gate is a gate with two or more inputs and outputs. The output of a two-input XOR gate assumes a HIGH state if one and only one input assumes a HIGH state i.e. the output is HIGH only if input A or input B is HIGH and the output is LOW when both the inputs are either HIGH or LOW. The logical symbol of the XOR is shown below –

*Fig. 11: XOR Gate Symbol*

The output of an XOR gate for two boolean variables can be represented by the following truth table –

The truth table of the XOR gate shows that the output is HIGH when any one, but not all of the inputs is 1 and when the both inputs are same i.e. either 0 or 1, the output is LOW. This exclusive feature eliminates a similarity to the OR gate. The truth table for XOR gate can be graphically represented by the following timing diagram –

*Fig. 12: XOR Gate Timing Diagram*

** Exclusive – NOR (XNOR) Gate** –

The XNOR gate performs the logical function which is the serial combination of the NOT and XOR Gates. The output of a XNOR gate assumes a HIGH state if all the input assumes either HIGH state or LOW state. If either input has a different logic state, the output of XNOR gate is LOW. The logical symbol of the XNOR is shown below –

*Fig. 13: XNOR Gate Symbol*

The output of an XNOR gate for two boolean variables can be represented by the following truth table –

The truth table for XNOR gate can be graphically represented by the following timing diagram –

* Fig. 14: XNOR Gate Timing Diagram*

These logic gates are the building blocks of any digital circuit. In the next tutorial, learn about theorems of boolean algebra and how a boolean expression can be minimized to Minterms and Maxterms, so, it can be implemented by two level interconnection of universal logic gates (NAND and NOR).

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