Mid-range FPGAs and System-on-Chip (SoC) FPGAs have played a major role in moving computer workloads to the network edge. Microchip Technology has helped fuel this transition with its award-winning FPGAs, delivering the first RISC-V-based FPGAs that provide twice the power efficiency of competing mid-range FPGAs — and feature a best-in-class design, operating system, and solutions ecosystem.
The company will be showing its solutions at the 2022 RISC-V Summit and previewing its PolarFire 2 FPGA silicon platform and RISC-V-based processor subsystem and software suite roadmap. It will also be discussing a RISC-V-based High-Performance Spaceflight Computing (HPSC) processor that it is developing for NASA and the aerospace and defense industry.
“Microchip was the first to offer FPGAs for power-efficient edge-compute segments, and the first to bring SoC FPGAs into volume production that support the RISC-V open Instruction Set Architecture,” said Shakeel Peera, VP of marketing for Microchip’s FPGA business unit. “At this year’s summit, we are extremely excited to showcase our production-ready PolarFire SoC family, partner ecosystem and solutions for today’s power-sensitive edge computing systems. An added bonus will be a sneak peek of where we are going next to deliver 15X more compute capability to our roadmap.”
The PolarFire FPGA and PolarFire SoC families already deliver the industry’s best thermal and power efficiency in the mid-range segment. Optimized for deploying systems with high compute performance in small form factors, the families have reduced the size and weight of power-constrained systems in applications including industrial imaging, robotics, AI-enabled medical systems, and smart defense and aerospace systems.
The PolarFire 2 family will go even further up the performance and power-efficiency curve and add new RISC-V-based high-performance compute elements. It also includes a design tool set that takes a new approach to system development, unlocking the full potential of these FPGAs and SoC FPGAs by eliminating the need for smart algorithm developers to understand the intricacies of the underlying FPGA hardware.
Microchip will also be showing its Mi-V solutions ecosystem for supporting RISC-V-based solution stack development. It provides 90%+ coverage for commercial and open-source Operating System (OS) and Real-Time OS (RTOS) packages, and includes other software, middleware and firmware offerings from Microchip and its Mi-V ecosystem partners.
RISC-V Summit attendees can see Microchip’s PolarFire family and Mi-V ecosystem, PolarFire 2 family and design tool suite preview, and HPSC offerings December 13-14, 2022, in Booth #PG5, Hall 2, at the San Jose McEnery Convention Center in San Jose, California.
Attendees can learn more about Microchip during the following presentations at the conference:
- “RISC-V Spotlight: Microchip’s RISC-V Journey to Deliver Innovation from Edge Compute to the Edge of the Solar System,” Bruce Weyer, corporate VP, FPGA, Microchip, on December 13 in Hall 3 from 11:00 to 11:10 a.m.
- “RISC-V Enabling High Performance Spaceflight Computing,” on December 14 in Hall 3 from 9:40 to 9:55 a.m.
For complete information about Microchip’s FPGA families click here.
Filed Under: Aerospace, Components, FPGA, News