Microsemi, an American company which manufactures semiconductors and system solutions for industrial markets, has recently become the first FPGA provider to roll out RISC-V as soft IP processor core. Apart from this, it’s also offering a comprehensive software tool chain for embedded designs. Interestingly, RISC-V (pronounced as Risk 5) isn’t a processor core; rather it’s an open source instruction set architecture (ISA) based on established reduced instruction set computing principles.
The company’s product i.e. RV32IM RISC-V core is offered for IGLOO2 FPGAs, SmartFusion2 system-on-chips (SoC) FPGAs, and RTG4. Besides, there is an Eclipse based SoftConsole integrated development environment (IDE) which is hosted on Linux platform and the Libero SoC Design Suite, thereby providing complete design support.
The main aim behind designing RISC-V is to utilise it for modern computerized devices such as a warehouse-scale cloud computers, high-end smartphones, as well as small embedded systems. Unlike other ISAs, RISC -V chips and software can be availed for multiple uses- be it manufacturing, design or sale. Moreover, contrary to other proprietary cores, this one is available for inspection addresses reliability and security concerns.
Citing an example of the implementation, for the 100 MHz SmartFusion2, RV32IM RISC-V core features a 5-stage pipeline that consumes just 12k logic elements while providing 1.1 Dhrystone MIPS (Million Instructions per second) per MHz.
As per Mr. Venki Narayanan, Senior Director of Software and Systems engineering for Microsemi’s SoC Products Group, “RISC-V is a great fit for implementing clean-slate processor capabilities for security, trust and reliability which are central to Microsemi’s solutions. We will continue our leadership position in this technology by further investigating in this architecture to ensure customers have long-term roadmap support.”
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