MIPS releases RISC-V i8500 processor supporting multi-cluster deployment

MIPS has announced that the MIPS I8500 processor is now sampling to lead customers. The processor was featured at GlobalFoundries’ Technology Summit in Munich, Germany. The I8500 is a data movement processor IP designed for real-time, event-driven computing platforms targeting hyperscale, storage, automotive, industrial, and communications infrastructure markets.

The MIPS I8500 incorporates a scalable multithreaded architecture with 4 threads per core and supports multi-cluster deployments that enable up to 24 threads per cluster. The processor provides low-latency, deterministic data movement with integrated security features. The architecture is designed for orchestrating packet flows across accelerators and enabling communication between compute blocks, humans, and networks. The processor’s design targets edge AI workloads with RVA23 profile readiness and support for both Linux and Real-Time operating systems to ensure software portability and ecosystem compatibility.

The processor enables data orchestration through rule-based packet classification for Smart NICs, DPUs, and backhaul processors in data centers and telecom networks. In industrial IoT and automation applications, it provides local protocol and routing processing for workloads requiring real-time control, prioritization, and secure processing. The architecture delivers deterministic data handling for predictive maintenance and AI-driven diagnostics applications.

The I8500’s deployment flexibility supports 5G/6G and edge computing environments through its multi-core, multi-cluster design configurations. The processor enables dynamic traffic management, encryption, and Quality of Service functions to maintain secure communication channels through programmable pipelines.

Customer evaluation of the MIPS I8500 Atlas Explorer Core Model is currently available, allowing software-hardware co-design to reduce design cycles and decrease time to market. MIPS will demonstrate the processor at the RISC-V Summit North America on October 22-23.