555 timer IC is commonly used in monostable mode to generate a pulse every time a trigger is given. The project described here uses NAND gate for monostable operation and thereby avoiding the need of 555 timer.
The circuit in the project uses IC 7400, which has four inbuilt NAND gates. Here we have used the first and second NAND gate of the IC 7400. Suppose, initially the trigger input T is High at a logic level "1" so that the output from first gate (U1) is Low at logic level "0". The resistor, R will cause the capacitor, C to charge or discharge. The output from the second NAND gate (U2), which is connected as an inverting NOT gate is also fed back to the input of U1,which is at logic level "1". Since both junction V1 and the output of U1 are both at logic "0" no current flows in the capacitor C and this results in the circuit being Stable and will remain in this state until the trigger input T changes.
If a logic level “0” pulse is now applied to the trigger input of gate U1the output of U1 will go high to logic “1”. Since the voltage across the capacitor cannot change instantaneously this will cause the junction V1 and also the inputs of U2 to go high, which in turn will make the output of the NAND gate U2 go low. The circuit will remain in this state even if the trigger input pulse T is removed. This is known as the Meta-stable state.
The voltage across the capacitor will now increase as the capacitor C charges up from the output of U1 at a time constant determined by the resistance and capacitance combination, until the junction at V1 reaches a logic “0” level causing the output of U2 to switch high again, which in turn causes the output of U1 to go low and the capacitor discharges under the influence of resistor R. The circuit is now back to its original stable state.
The length of the output time period is determined by the capacitor/resistor combination and is given as the Time Constant T = 0.7RC of the circuit in seconds.
Filed Under: 555 Timers, Electronic Projects