N-bit Ring Counter made using VHDL

A ring counter as the name depicts is a closed loop. Normally in counters their is an increment or decrement in the output depending on if its a up or down counter. In contrast to up and down, ring is some what a fixed counter. Only a specified number of bits revolve around in a fixed length of ring. Its same like a train revolving on a circular track. The buggies of train are fixed and the length of the track is also fixed. Lets see an example which will clear all the concepts about ring counter and its purpose.

Ring counter example

In the below figure the size of the variable is fixed which is 5 bits. We want to revolve a fixed single-bit in 5 bit variable. Initially bit-1 is 1. In the next clock cycle the 1 is moved or shifted to bit-2 position and bit-1 is replaced with 0. This whole process shifts the 1 to next bit on each successive clock cycle. This movement of the 1 is also know as shifting.

5-bit ring counter bit shifting

After reaching the last bit-N the 1 moves to bit-0 because the ends of the counter are joined together to form a ring. This toplogy is know as ring counter. Below figure is about how the bit moves in ring.

Ring counter bit shifting in circular path

The size of the variable can be increased to N-bit. The size of revolving bits can also be increased depending on the requirement. At last the clock cycles can also be varied depending on the requirements.

N-bit ring counter in vhdl

I am going to design a N-bit ring counter in vhdl. Only just a single bit ‘1’ is revolved around ‘0’. Bit is forwarded or shifted on each clock cycle. Reset and enable is also part of the project. Reset is active high and enable is also active high. Both reset and enable are synchronous. I assume that you are familiar with reset and enable meaning also you know about what is synchronous and asynchronous? If you are not familiar with these therms than i would suggest to please first know what they mean. Other wise you will find it hard to understand code below.

N-bit counter tested on 4-bits

I designed and N-bit ring counter. But for testing we have to input the size of the variable. I selected 4. The purpose of selecting the small number is just to show in simulation that the output of ring counter is repeating and following a circular path. You can see the ring counter simulation output below. On each clock cycle 1 is shifting and exactly when it reaches bit-3 it jumps to bit-0 following a circular path.Enable is high and reset is disabled.

4-bit Ring Counter in vhdl

Ring counter vhdl code

First i imported the desired libraries. I expect you know about these libraries. Then the main entity name is declared as Ring_count_N. A generic integer variable is defined first in entity. This integer N is actually the size of the variable. For 4-bit ring counter i assigned it value 4. Next the input/output ports of the entity are defined. You can see that the output port size is dependent on the integer variable N. If you want to decrease or increase the size of the variable or ring counter simple replace 4 with your desired number.

In the architecture i made an FSM(finite state machine) for the logic and implemented it. Current state and next state signals are defined. These signals must be of the same size of variable since they hold the output. In body of the architecture a process is generated. This process sensitive to clock.

In the process block the statement Clk = ‘1’ AND Clk’EVENT checks if the positive edge of the clock is arrived. If arrived the control moves in the if statement and checks the next condition Rst=’1′. This statement means if reset is 1 then Currstate <= (0 => ‘1’,OTHERS =>’0′) which assigns Currstate=”1000″. So the system is reset and Currstate value is “1000”. If the reset is not 1 then the control jumps to ELSIF(En=’1′) statement. This statement checks if enable is active. If so Nextstate value is assigned to Currstate.

The process ends up here. The next two statements are the real brain of the whole logic. The first statement picks the bit-0 of currstate and concatenate it with the rest. Then assign it to the nextstate.

What happens is on reset the currstate is 1000 as explained above. The next state is 0100 by the statement Nextstate <= Currstate(0) & Currstate(N-1 DOWNTO 1). & is a concatinate operator. This nextstate is assigned to currstate in the next clock cycle in which enable is activated and reset is disabled.

Finally the output is assigned the Currstate output <= Currstate;. Ring counter top level entity is shown in the figure below. The final RT level architecture is composed of four flip flops. The RT level architecture is not shown because the figure was occupying two much space and its hard to clearly see the RT components in the figure.

Ring counter top level entity

Ring counter vhdl test bench

The test bench is simple. Ring counter is instantiated as a component. A single process is used for clock generation. Clock cycle is 20 ns. A second process is used to reset the counter and activate the enable port.

In the above code the statement Rst<=’1′,’0′ after 5ns reset ring counter and after 5 ns it disables the reset and enables the enable port.

Project files