New OptiMOS power MOSFET package enables innovative source-down technology

High-power density, optimized performance, and ease-of-use are key requirements when designing modern power systems. To offer practical solutions for design challenges in end applications, Infineon Technologies has launched a new generation of OptiMOS source-down (SD) power MOSFETs.

These devices come in a PQFN 3.3 x 3.3 mm² package and a wide voltage class ranging from 25 V up to 100 V.

This package sets a new standard in power MOSFET performance, offering higher efficiency, higher power density, superior thermal management, and a low bill-of-material. The PQFN addresses applications including motor drives, SMPS for server, telecom, OR-ing, and battery-management systems.

Compared to the standard drain-down concept, the latest source-down package technology enables a larger silicon die in the same package outline. In addition, the losses contributed by the package — limiting the overall performance of the device — can be reduced. This enables a reduction in R _DS(on) by up to 30 percent compared to the top drain-down packages.

The benefit at the system level is a shrink in the form factor with the possibility to move from a SuperSO8 5 x 6 mm² footprint to a PQFN 3.3 x 3.3 mm² package with a space reduction of about 65 percent. This allows for the available space to be used more effectively, enhancing the power density and system efficiency in the end system.

Additionally, in the SD concept, the heat is dissipated directly into the PCB through a thermal pad instead of over the bond wire or the copper clip. This improves the thermal resistance R _thJC by more than 20 percent — from 1.8 K/W down to 1.4 K/W, enabling simplified thermal management.

Infineon offers two different footprint versions and layout options: the SD standard-gate and the SD center-gate. The standard-gate layout simplifies the drop-in replacement of drain-down packages, while the center-gate layout enables optimized and easier parallelization. These two options can bring optimal device arrangement in the PCB, optimized PCB parasitics, and ease-of-use.