Point2 Technology releases 3.0 W smart retimer SoC for 800G/1.6T applications

Point2 Technology announced its P1B121 Smart Retimer system-on-chip (SoC) for Active Electrical Cable (AEC) applications in AI/ML data centers. The chip integrates eight unidirectional SerDes channels supporting 112G PAM4 and 56G NRZ data rates and consumes 3.0 W of power for 112G PAM4 operation.

The solution addresses growing data center power demands, as AI/ML workloads now account for 20% of data center electricity, according to EPRI. U.S. data center electricity usage is projected to reach 9.1% of total generation by 2030.

The P1B121 operates with three nanoseconds latency in 800 gigabit and 1.6 Terabit AEC applications. It serves top-of-rack switch connections to servers, rack-to-rack links, and accelerator-to-accelerator compute fabric connectivity.

The SoC features a BER-aware architecture correlating chip error rates to circuit block power consumption. This enables AECs to use smaller copper wire gauges, reducing cable volume while extending length compared to traditional copper cabling.

The chip includes adaptable line equalization, 2x56G to 1x112G bounded Gearbox transposition, programmable FIR filters and pre-emphasis for serialization, and adjustable CTLE and DFE for de-serialization.