Registers - DE Part 19

In the previous tutorial, the concept and construction of flip flops was discussed. The flip flops are essential building block of any synchronous or clocked sequential circuit. Without flip flops, a clocked sequential circuit is reduced to a combinational circuitry. Even flip flops alone are considered sequential circuits. There are two types of sequential circuits that are solely constructed from the flip flops – Registers and Counters.

A register is a group of flip flops having a common clock signal and capable of storing or retaining binary information. Each flip flop in a register is a binary cell capable of storing one bit of information. An n – bit register has a group of n flip flops and is capable of storing any binary information containing n bits. The register is mainly used for storing and shifting binary data entered into it from an external source.

The registers are used in wide range of digital systems like multipliers, dividers, memories, microprocessor, etc. A counter is a register that goes through predetermined sequence of states. While register has no specific sequence of states expect in certain specialized applications.

For example, below is a 4-bit register constructed by 4 D Flip Flops. All the four flip flops of the register have a common clock signal and a common reset signal (The D Flip Flops here have a reset input to set the output to 0 by default). The parallel data from external source is feed to the data input pins of the D flip flops. When the clock pulse (common to all flip flops) is triggered, it is transferred at the output pins of the D flip flops. The reset input (common to all flip flops) is active low which by default is maintained at 1. When 0 is applied to the active low reset input, all the flip flops are reset to an output of 0.

Fig. 1: Memory Register Logic Gate Diagram

The register shown above is a parallel register and is the simplest type of register. Such registers are commonly used in microprocessors and microcontrollers for storing the binary data. These types of register transfer data from source to destination in parallel mode which is preferred for faster computing in microprocessor and microcontroller designs. These type of registers that are used to store binary information are called memory registers.

Shift Registers –

The other type of registers commonly used in digital systems are Shift registers. The shift registers are used for shifting binary data within a digital system. By shifting data, the binary data is stored in a destination register (which itself may be a shift register) within a digital system. A shift register can shift binary information either in left direction (left shifting), right direction (right shifting), left in but right out (rotation) or both left and right (bidirectional shifting). The data in a register may be input either serial or parallel and can also be output either serial or parallel. Based on the serial or parallel mode of data input and output in the register, shift registers can be classified as of the following four types –

1) Serial – in to Serial – out (SISO) :- In this type of shift register, the binary data is input, shifted and output serially in either left or right direction one bit at a time under a common clock signal.

2) Serial – in to Parallel – out (SIPO) :- In this type of shift register, the binary data is input and shifted serially in either left or right direction one bit at a time but is output parallel all together under a clock signal.

3) Parallel – in to Serial – out (PISO) :- In this type of shift register, the binary data is input all together in parallel mode but is shifted and output serially in either left or right direction one bit at a time under a clock signal.

4) Parallel – in to Parallel – out (PIPO) :- In type of shift register, the binary data is input as well as shifted and output in parallel mode all together under a clock signal. This type of shift register is same as a memory register build from D Flip Flops.

Unlike memory registers which are constructed by connecting the flip flops in parallel fashion, the shift registers are constructed by connecting the flip flops in cascade in a daisy chain style. The shift registers are exclusively build from D Flip Flops only. The size of shift register is always same as the size of the binary words used in a digital system. Like a 4-bit digital system will have 4-bit words and so use 4-bit shift registers. Similarly, 8-bit digital system will have 8-bit words and so use 8-bit shift registers. It must be noted that all the flip flops of a shift register have common clock signal. It is common clock signal that makes the shift registers synchronous (sequential) circuits.

Serial-In Serial-Out (SISO) Shift Register – A Serial-In Serial-out shift register accepts data serially, i.e. one bit at a time on a single input line. It produces the stored information on its single output also in serial form. Data may be shifted left from MSB to LSB using shift left register or shifted right from LSB to MSB using shift right register. The SISO shift register is constructed by connecting D Flip Flops in Cascade manner as follow –

Fig. 2: Serial-In Serial-Out Shift Register Logic Gate Diagram

Suppose a 4-bit binary word 1111 has to be shifted in SISO shift register. Before the arrival of clock signal, let Q3 Q2 Q1 Q0 = 0000. This being right shift register, LSB of the binary word will be entered to the input data bus (Din) first. So Din = D3 = 1. On the first falling edge of clock, the Flip-Flop-3 is set, and stored word in the register is Q3Q2 Q1 Q0 = 1000.

Fig. 3: 4-Bit Serial-In Serial-Out Shift Register States on First Pulse

On the arrival of the second clock pulse, the next bit is passed to D_in. So D_in = 1 while Q3 is 1. As soon as the next negative edge of the clock hits, FF-3 will set by Din being 1 and FF-2 will set to 1. So, the stored word changes to Q₃ Q₂ Q₁ Q₀ = 1100.

Fig. 4: 4-Bit Serial-In Serial-Out Shift Register States on Second Pulse

On the arrival of the third clock pulse, the next bit to be stored i.e. 1 is passed to D_in. So D_inis 1 while Q3 = 1 and Q2 = 1. As soon as the third negative clock edge hits, FF-3 will be set to 1 by D_in being 1, FF-2 will set to 1 and FF-1 will be set to 1. So, the stored word changes to Q₃ Q₂ Q₁ Q₀ = 1110.

Fig. 5: 4-Bit Serial-In Serial-Out Shift Register States on Third Pulse

On the arrival of the fourth and last clock pulse, the MSB i.e. 1 is passed to D_in. So D_inis 1 while Q3 = 1, Q2 = 1 and Q1 = 1. As soon as the fourth negative clock edge hits, FF-3 will be set to 1 by D_in being 1, FF-2 will set to 1, FF-1 will be set to 1 and FF-0 will set to 1. So, the stored word changes to Q₃ Q₂ Q₁ Q₀ = 1111.

Fig. 6: 4-Bit Serial-In Serial-Out Shift Register States on Fourth Pulse

The operation of the shift register can be summarized by the following function table –

Usually in digital systems, an additional shift control input is provided with the shift registers. The shift control input and clock pulse are applied to AND gate which are connected to the clock line of the shift registers. So, the clock pulse is applied to the registers only when the shift control input is set to HIGH state. When a binary word has to be transferred to the shift register, a pulse of duration equal to the sum of durations of all pulses required to shift entire word is applied at the shift control input. Like if 4-bit word has to be shifted in a 4-bit shift register, a pulse of duration equal to 4 pulses of clock signal is applied to shift control input. This way, only when shift control input is HIGH, the binary word is shifted while for rest of clock pulses, the register remains undisturbed. The shift control input is essentially required in a digital system where there may be other sequential circuits operating under a master clock. By using shift control input, the binary words can be shifted in registers when required irrespective of regular master clock pulse train.

Serial-In Parallel-Out (SIPO) Shift Register – A Serial-In Parallel-Out Shift register consists of one serial input and outputs are taken from all the flip flops in parallel mode. In this register, data is shifted in serially but shifted out in parallel mode. In order to shift the data out in parallel, it is necessary to have all the data available at the outputs at the same time. Once the data is stored, each bit appears on its respective output line and all the bits are available simultaneously, rather than on a bit-by-bit basis as with the serial output. A Serial-In Parallel-Out Shift register can be constructed using D Flip Flops as follow –

Fig. 7: Serial-In Parallel-Out Shift Register Logic Gate Diagram

Parallel-In Serial-Out (PISO) Shift Register – For a register with parallel data inputs, the bits are entered simultaneously into their respective flip – flops rather than a bit – by – bit basis on one line.

Like in a 4-bit Parallel-In Serial-Out register, there are four parallel data – input lines say designated as A, B, C and D and SHIFT/LOAD is a control input that allows the four bit of data at A, B, C and D inputs to enter into the register in parallel or shift the data in serial. When SHIFT/LOAD is LOW, AND gates G1 through G3 are enabled, allowing the data at parallel inputs i.e. A, B, C and D to the Data inputs of the respective flip-flops. The A input is directly connected to the D input of the first flip – flop. When a clock pulse is applied, the flip – flops with D = 1 will be SET and the flip – flops with D = 0 will be RESET, thereby storing all four bits simultaneously.

When SHIFT/LOAD is HIGH, AND gates G1 through G3 are disabled and the remaining AND gates G4 through G6 are enabled, allowing the data bits to shift right from one stage to the next. The OR gates allow either the normal shifting operation or the parallel data-entry operation, depending on which the AND gates are enabled by the level on the SHIFT/LOAD input. A Parallel-In Serial-Out shift register can be constructed using D Flip Flops as follow –

Fig. 8: Parallel-In Serial-Out Shift Register Logic Gate Diagram

Parallel-In Parallel-Out (PIPO) Shift Register – In this type of register, data inputs can be shifted either in or out of the register in parallel. The parallel entry of the data is carried out as in a Parallel-In Serial-Out shift register. Also, in this register, there is no interconnection between successive flip flops since no serial shifting is required. Therefore, the moment the parallel entry of the input data is accomplished, the respective bits will appear at the parallel outputs. A simple 4 – bit Parallel-In Parallel-Out shift register constructed using D flip flops is as follow –

Fig. 9: Parallel-In Parallel-Out Shift Register Logic Gate Diagram

Here the parallel inputs to be entered should be applied at A, B, C and D inputs which are directly connected to delay inputs of respective flip – flops. Now on applying clock pulse, these inputs are entered into the register and are immediately available at the outputs Q1, Q2, Q3, and Q4. This type of shift register is similar to a memory register constructed using D Flip Flops.

Universal Shift Registers – The universal shift registers can shift binary data in any direction and can input and output it both serially as well as parallel. It has additional control inputs to specify the direction of the data movement, input mode and output mode.

In the next tutorial, learn about the other sequential circuit solely built by flip-flops – Counters.