Verilog Tutorial 12: How to design 8-bit parity generator and checker circuits in Verilog

Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial. Follow the full series here.

In the previous Verilog Tutorial – 11, we learned how to design half and full-subtractor circuits in Verilog.

In this tutorial, we’ll:

1. Write a Verilog program to build an 8-bit parity generator and checker circuits
2. Verify the program’s output waveform (digital circuit) with truth tables for the parity generator and parity checker circuits

The half-subtractor circuit

Truth table

Next, let’s write the Verilog program, compile and simulate it, and get the output in a waveform. We’ll also verify the output waveforms with the given truth table.

First, it’s important to review the step-by-step procedure provided in VHDL Tutorial – 3. In that tutorial, we learn how to design a project, edit and compile a program, create a waveform file, simulate the program, and generate the final output waveforms.

Verilog program

Gate-level modeling:

module parity_gen(even_p,odd_p,d);
 output even_p,odd_p;
 input [7:0] d;
 wire t1,t2,t3,t4,t5,t6;
  xor(t1,d[0],d[1]);
  xor(t2,d[2],t1);
  xor(t3,d[3],t2);
  xor(t4,d[4],t3);
  xor(t5,d[5],t4);
  xor(t6,d[6],t5);
  xor(even_p,d[7],t6);
  not(odd_p,even_p);
endmodule

Dataflow modeling:

module parity_gen(even_p,odd_p,d);
 output even_p,odd_p;
 input [7:0] d;
 wire t1,t2,t3,t4,t5,t6;
 assign t1 = d[0] ^ d[1];
 assign t2 = d[2] ^ t1;
 assign t3 = d[3] ^ t2;
 assign t4 = d[4] ^ t3;
 assign t5 = d[5] ^ t4;
 assign t6 = d[6] ^ t5;
 assign even_p = d[7] ^ t6;
 assign odd_p = ~even_p;
endmodule

Now, compile the above program, creating a waveform file with all of the necessary inputs and outputs that are listed, and simulate the project. 

Here are the results…

Waveform simulation

Be sure to verify the ‘even_p’ and ‘odd_p’ output waveforms with the D0-D7 input data. For example, as shown above, for ‘1111 1011’ the even_p output is ‘1’ and the odd _p output is ‘0.’ Whereas, for ‘1011 1110,’ the even_p output is ‘0’ and the odd_p output is ‘1.’

Next, let’s build the 8-bit parity checker circuit.

The 8-bit parity checker circuit

Truth table

Verilog program

Gate-level modeling:

module parity_chk(p,e,d);
 output e;
 input [7:0] d,p;
 wire t1,t2,t3,t4,t5,t6,t7;
  xor(t1,d[0],d[1]);
  xor(t2,d[2],t1);
  xor(t3,d[3],t2);
  xor(t4,d[4],t3);
  xor(t5,d[5],t4);
  xor(t6,d[6],t5);
  xor(t7,d[7],t6);
  xor(e,p,t7);
endmodule

Dataflow modeling:

module parity_gen(p,e,d);
 output e;
 input [7:0] d,p;
 wire t1,t2,t3,t4,t5,t6,t7;
 assign t1 = d[0] ^ d[1];
 assign t2 = d[2] ^ t1;
 assign t3 = d[3] ^ t2;
 assign t4 = d[4] ^ t3;
 assign t5 = d[5] ^ t4;
 assign t6 = d[6] ^ t5;
 assign t7 = d[7] ^ t6;
 assign e = p ^ t7;
endmodule

Simulation waveform

Now, verify the ‘e’ output waveform against the parity input ‘p’ and the D0-D7 data. As shown aboive, for ‘0101 1011’ and parity ‘1,’ the error output is ‘1.’ Whereas, for ‘0100 1010′ and parity ‘0,’ the output is ‘0.’

In next tutorial, we’ll learn how to design 8×3 encoder and 3×8 decoder circuits by using VHDL.

 

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Filed Under: Tutorials
Tagged With: tutorial, vdhl, verilog
 

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