How-to-design-a-3x8-decoder-and-an-8x3-encoder-in-vhdl

Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial. Follow the full series here.

In the previous Verilog Tutorial – 12, we learned how to design half and full-subtractor circuits in Verilog.

In this tutorial, we’ll:

Write a Verilog program for building circuits for a 3×8 decoder and an 8×3 encoder
Verify the output waveform of the program (digital circuit) with the given truth tables for the encoder and decoder circuits

The 3×8 decoder circuit:

Truth table

Next, let’s write the Verilog program, compile and simulate it, and get the output in a waveform. We’ll also verify the output waveforms with the given truth table.

First, it’s important to review the step-by-step procedure provided in VHDL Tutorial – 3. In that tutorial, we learn how to design a project, edit and compile a program, create a waveform file, simulate the program, and generate the final output waveforms.

Verilog program

Gate-level modeling:

module decoder3x8(a,b,c,d);
input a,b,c;
   output [0:7] d;
   wire a_not,b_not,c_not;
   not(a_not,a);
   not(b_not,b);
   not(c_not,c);
   and(d[0],a_not,b_not,c_not);
   and(d[1],a,b_not,c_not);
and(d[2],a_not,b,c_not);
   and(d[3],a,b,c_not);
     and(d[4],a_not,b_not,c);
     and(d[5],a,b_not,c);
     and(d[6],a_not,b,c);
     and(d[7],a,b,c);
   endmodule

Dataflow modeling:

module decoder3x8(a,b,c,d);
input a,b,c;
output [0:7] d;
     assign d[0] = ~a & ~b & ~c;
     assign d[1] = a & ~b & ~c;
     assign d[2] = ~a & b & ~c;
     assign d[3] = a & b & ~c;
     assign d[4] = ~a & ~b & c;
     assign d[5] = a & ~b & c;
     assign d[6] = ~a & b & c;
assign d[7] = a & b & c;
endmodule

Now, compile the above program, creating a waveform file with all of the necessary inputs and outputs that are listed, and simulate the project.

Here are the results…

Waveform simulation

Be sure to verify the D0-D7 output. You’ll note that only one output is high at a time. All of the others are then low, as per the given input A0-A1-A2 combinations from ‘000’ to ‘111.’

Next, let’s build the 8×3 encoder circuit.

The 8×3 encoder circuit:

Truth table

Verilog program

Gate-level modeling:

module encoder8x3(a,b,c,d);
input [0:7] d;
output a,b,c;
     or(c, d[1], d[3], d[5], d[7]);
     or(b, d[2], d[3], d[6], d[7]);
     or(a, d[4], d[5], d[6], d[7]);
endmodule

Dataflow modeling

module encoder8x3(a,b,c,d);
input [0:7] d;
output a,b,c;
     assign c = d[1] | d[3] | d[5] | d[7]);
     assign b = d[2] | d[3] | d[6] | d[7]);
     assign a = d[4] | d[5] | d[6] | d[7]);
endmodule

Simulation waveforms

As shown above, the input output waveforms looks similar to those of the decoder. This is because the encoder is simply the reverse of the decoder. So the input becomes output, and vice versa.

In the encoder example, when D7’s input is ‘1,’ the outputs are ‘a = 1,’ ‘b=1,’ and ‘c=1.’ You can verify other combinations based on the truth table.

In next tutorial, we’ll design circuits for an 8×1 multiplexer and a 1×8 de-multiplexer by using Verilog.