Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial.
In the previous tutorial – VHDL tutorial 16 – we designed a D flip-flop circuit by using VHDL.
For this project, we will:
- Write a VHDL program to build a JK flip-flop circuit
- Verify the output waveform of the program (the digital circuit) with the flip-flop truth table.
The JK flip-flop with a preset and a clear circuit:
- Note 1: when J=1 and K=1, the Q output toggles every time (from 0 to 1 and 1 to 0)
- Note 2: when J=0 and K=0, the Q output retains its previous state
Now, let’s write, compile, and simulate a VHDL program. Then, we’ll get the output in waveform and verify it with the given truth table.
Before starting, be sure to review the step-by-step procedure provided in VHDL Tutorial – 3 to properly design the project, as well as edit and compile the program and the waveform file, including the final output.
Here. we’ve used a behavioral modeling style to write the VHDL program and build the flip-flop circuit because it’s the model preferred for sequential digital circuits.
entity JK_flip_flop is
port (clk,J,K,prs,clr : in std_logic;
Q: out std_logic;
Qnot : out std_logic);
architecture JKFF_arch of JK_flip_flop is
signal nxt_state,prv_state: std_logic;
signal input: std_logic_vector(1 downto 0);
input <= J & K;
process(clk, prs,clr) is
if (clr=’1′) then
nxt_state <= ‘0’;
elsif (prs=’1′) then
nxt_state <= ‘1’;
elsif (clk’event and clk=’1′) then
case (input) is
when “10” => nxt_state <= ‘1’;
when “01” => nxt_state <= ‘0’;
when “00” => nxt_state <= prv_state;
when “11” => nxt_state <= not prv_state;
when others => null;
Q <= nxt_state;
Qnot <= not nxt_state;
prv_state <= nxt_state;
Next, compile the above program, creating and then saving a waveform file with all of the necessary inputs and outputs that are listed (and be sure to apply all of the different input combinations). Then, simulate the project. You should get the following result…
- Case 1: when prs=1 -> Q = 1 and Qnot = 0 (the flip-flop is set)
- Case 2: when clr=1 -> Q=0 and Qnot = 1 (the flip-flop is clear)
- Case 3: when J=1, K=0 and clk=1 – > Q = 1 and Qnot = 0
Be sure to verify the different input-output combinations with the given truth table.
In the next tutorial, we’ll learn how to build a T flip-flop circuit by using VHDL.
Filed Under: VHDL