VHDL Tutorial – 19: Designing a 4-bit binary counter using VHDL

Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial.

In the previous tutorial, VHDL – 18, we designed a T-flip flop using VHDL.

For this project, we will:

Write a VHDL program a VHDL program to build a 4-bit binary counter
Verify the output waveform of the program (the digital circuit) with the counter’s truth table

The 4-bit binary counter

Truth table

Now, let’s write, compile, and simulate a VHDL program. Then, we’ll get the output in waveform and verify it with the given truth table.

Before starting, be sure to review the step-by-step procedure provided in VHDL Tutorial – 3 to design the project. It will ensure that you properly edit and compile the program and the waveform file, as well as the final output.

VHDL program

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity counter is
Port ( rst,clk : in std_logic;
o: out std_logic_vector(0 to 3));
end counter;

architecture count_arch of counter is
   signal count : std_logic_vector(0 to 3);
    begin
      process(rst,clk)
        begin
          if (rst = ‘1’) then count <= “0000”;
          elsif (clk’event and clk = ‘1’) then count <= count + 1;
          end if;
         end process;
         o <= count;
      end count_arch;

To refresh your memory about how this works, go through the first two VHDL tutorials (1 and 2) of this series.

Next, compile the above program, creating and then saving a waveform file with all of the necessary inputs and outputs that are listed (ensuring you apply all of the different input combinations). Then, simulate the project. You should get the following result…

Simulation waveform

It can easily be observed from the waveform that when rst=1, the output ‘o’ is 0 (0000). Then, it increases in increments with each positive edge of the clock: 0001(1), 0010(2), 0011(3), etc.

Now, let’s build the up-down counter. It has an additional input signal for the “up_down,” so that when:

The up_down = 0 ->, the counter counts up from 0, 1, 2, 3,…15, etc.
The up_down = 1 ->, the counter counts down from 15, 14, 13, … to 0.

The up-down binary counter (4-bit)

VHDL program

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity counter is
Port ( rst,clk,up_dwn : in std_logic;
o: out std_logic_vector(0 to 3));
end counter;

architecture count_arch of counter is
   signal count : std_logic_vector(0 to 3);
    begin
      process(rst,clk)
        begin
          if (rst = ‘1’) then count <= “0000”;
          elsif (clk’event and clk = ‘0’) then
           if (up_dwn = ‘1’) then count <= count – 1;
           else   count <= count + 1;
          end if;
         end if;
         end process;
         o <= count;
      end count_arch;

Simulation waveforms

As you can see from this figure, when the up_dwn = 0, the count increases in increments with each negative edge of the clock. Then, when the up_dwn = 1, the count decreases. These examples are highlighted in red and blue, respectively.

In next tutorial, we’ll build a binary-to-gray and a gray-to-binary code converter using VHDL.