VHDL Tutorial – 22: Designing a 1-bit & an 8-bit comparator by using VHDL

Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial.

In the previous tutorial, VHDL Tutorial – 21, we designed an 8-bit, full-adder circuit by using VHDL.

In this tutorial, we will:

Write a VHDL program that builds a 1-bit and an 8-bit comparator circuit
Verify the output waveform of the program (digital circuit) with comparator circuit operation

The 1-bit comparator circuit

Truth table

Now, let’s write, compile, and simulate a VHDL program. Then, we’ll get the output in waveform and verify it with the given truth table.

Before starting, be sure to review the step-by-step procedure provided in VHDL Tutorial – 3 to design the project. It will ensure that you properly edit and compile the program and the waveform file, as well as the final output.

VHDL program

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity comparator_1bit is
Port ( A,B : in std_logic;
G,S,E: out std_logic);
end comparator_1bit;

architecture comp_arch of comparator_1bit is
begin
   G <= A and (not B);
   S <= (not A) and B;
   E <= A xnor B;
end comp_arch;

It may help to review the first two VHDL tutorials (1 and 2) of this series to refresh you memory about how this works.

Next, compile the above program, creating and then saving a waveform file with all of the necessary inputs and outputs that are listed (ensuring you apply all of the different input combinations). Then, simulate the project. You should get the following result…

As per this figure, the output of ‘G’ and ‘E’ are highlighted in red and blue, respectively, for A>B and A=B.

Next, let’s expand this from a 1-bit to an 8-bit comparator. To do so using VHDL, we’ll employ a behavioral modeling style because it’s easier than the two other styles.

The 8-bit comparator VHDL program

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity comparator_8bit is
Port ( A,B : in std_logic_vector(0 to 7);
G,S,E: out std_logic);
end comparator_8bit;

architecture comp_arch of comparator_8bit is
begin
   process
     begin
if A=B then
           G <= ‘0’;
           S <= ‘0’;
           E <= ‘1’;
       elsif A>B then
           G <= ‘1’;
           S <= ‘0’;
           E <= ‘0’;
      elsif A<B then
           G <= ‘0’;
           S <= ‘1’;
           E <= ‘0’;
      end if;
    end process;
end comp_arch;

Simulation waveform

As shown in this figure, the three results are highlighted in red, blue, and green, representing A>B, A<B, and A=B.

This is the final tutorial of this VHDL series. You can find additional programs for different digital circuits online and practice them to get more “hands-on” experience with VHDL programming. Keep learning and you’ll keep progressing!