Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial.
In previous tutorial VHDL tutorial – 10, we had designed half and full-adder circuits using VHDL.
In this tutorial, we will:
- Write a VHDL program to build half and full-subtractor circuits
- Verify the output waveform of program (digital circuit) with the truth tables for the half and full-subtractor circuits
Half-subtractor circuit
Truth table
Now, let’s write, compile, and simulate a VHDL program to get a waveform output. Then, we’ll verify the waveform output with the given truth table.
Before starting, be sure to review the step-by-step procedure provided in VHDL Tutorial – 3 to properly design the project, as well as edit and compile the program and the waveform file, including the final output.
VHDL program:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity half_sub is
port ( a,b : in std_logic;
dif,bo: out std_logic
);
end half_sub;
architecture sub_arch of half_sub is
begin
dif <= a xor b;
bo <= (not a) and b;
end sub_arch;
Note:
- The “entity” describes the input-output connections of the digital circuit. As per the circuit given here, you’ll note that there are two inputs (‘a’ and ‘b’) and two outputs (‘dif’ and ‘bo’).
- The “architecture” describes the operation of the circuit, which means how the output is generated from the given input.
To refresh your memory about how this works, go through the first two VHDL tutorials (1 and 2) of this series.
Next, compile the above program, creating a waveform file with all of the necessary inputs and outputs that are listed, and simulate the project. You should get the following result…
Simulation waveform
Verify the ‘dif’ and ‘bo’ output waveforms with the given truth table. For a=1 and b=0 inputs, the outputs are bo=0 and dif=1, which are highlighted in image.
Next, let’s move onto the full-subtractor circuit and its design.
Full subtractor circuit
Truth table
Let’s write the VHDL program for this circuit. In previous tutorial, we designed the full-adder circuit using a structural-modeling style for the VHDL programming. We’ll use the same modeling style to design the full subtractor.
We’ll build the full subtractor circuit by using the half-subtractor circuit and the “OR gate” as components (or blocks). In the circuit diagram you can see the full-subtractor circuit consist of two half-adder and an OR gate.
VHDL program
library IEEE;
Use IEEE. STD_LOGIC_1164.all;
entity full_sub IS
port (a,b,bin :in STD_LOGIC;
dif,bout : out STD_LOGIC);
end full_sub;
———————–architecture of full subtractor————-
architecture FS_arch of full_sub is
—————————–half adder component————————–
component half_sub is
port (p,q :in STD_LOGIC;
dif,bo: out STD_LOGIC);
end component;
———————or gate component————————-
component or_gate is
port (p1,q1 :in STD_LOGIC;
r1: out STD_LOGIC);
end component;
——————————-
signal d1,b1,b2 : STD_LOGIC;
begin
w1: half_sub port map (a,b,d1,b1);
w2: half_sub port map (d1,bin,dif,b2);
w3: or_gate port map (b1,b2,bout);
end FS_arch;
————————– half subtractor program ————————
library IEEE;
Use IEEE. STD_LOGIC_1164.all;
entity half_sub is
port (p,q : in STD_LOGIC;
dif,bo : out STD_LOGIC);
end half_sub;
architecture HS_arch of half_sub IS
begin
dif <= p xor q;
bo <= (not p) and q;
end HS_arch;
—————————–or gate program——————————
library IEEE;
Use IEEE. STD_LOGIC_1164.all;
entity or_gate is
port (p1,q1:in STD_LOGIC;
r1: out STD_LOGIC);
end or_gate;
architecture or_g of or_gate IS
begin
r1 <= p1 or q1;
end or_g;
To compile the above program:
- Create the waveform file with all of the inputs and outputs listed
- Apply the different input combinations
- Save the waveform file and simulate the project
You should get this result…
Simulation waveforms
Compare the outputs of the ‘dif’ and ‘bout’ with the given truth table. In the above diagram, one case is highlighted as a=0, b=1, and bin=0 with the outputs of dif=1 and bout=1.
In the next tutorial, we’ll learn how to design an 8-bit parity generator and parity checker circuits by using the VHDL.
