VHDL Tutorial – 12: Designing an 8-bit parity generator and checker circuits

Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial.

In the previous tutorial VHDL tutorial – 11, we learned how to design half and full-subtractor circuits by using the VHDL.

In this tutorial, we will:

• Write a VHDL program to build an 8-bit parity generator and checker circuits
• Verify the output waveform of the program (as a digital circuit) with the truth table of the parity generator and parity checker circuits

The 8-bit parity generator circuit

Truth table

Now, let’s write, compile, and simulate a VHDL program to get a waveform output. Then, we’ll verify the waveform output with the given truth table.

Before starting, be sure to review the step-by-step procedure provided in VHDL Tutorial – 3 to properly design the project, as well as edit and compile the program and the waveform file, including the final output.

VHDL program

library ieee;
use ieee.std_logic_1164.all;
entity parity is
      port( data:in bit_vector(7 downto 0);
                  even_p,odd_p: out bit);
end parity;
architecture parity_gen of parity is
signal temp : bit_vector(5 downto 0);
  begin
    temp(0)<=data(0) xor data(1);
    temp(1)<=temp(0) xor data(2);
    temp(2)<=temp(1) xor data(3);
    temp(3)<=temp(2) xor data(4);
    temp(4)<=temp(3) xor data(5);
    temp(5)<=temp(4) xor data(6);
    even_p <= temp(5) xor data(7);
    odd_p <= not(temp(5) xor data(7));
end parity_gen;

Note:

• The “entity” describes the input-output connections of the digital circuit. As per the given circuit here, there is an 8-bit data input of ‘d0-d7’ and two outputs of ‘even_p’ and ‘odd_p.’
• The “architecture” describes the operation of the circuit, which means how the output is generated from the given input.

To refresh your memory about how this works, go through the first two VHDL tutorials (1 and 2) of this series.

Next, compile the above program, creating a waveform file with all of the necessary inputs and outputs that are listed, and simulate the project. You should get the following result…

Verify the ‘even_p’ and ‘odd_p’ output waveforms with the input data of ‘D0-D7.’ For example, as highlighted in the diagram, for the input “1111 1011,” the even_p output is ‘1’ and the odd _p output is ‘0.’ For the input “1011 1110,” the even_p output is ‘0’ and the odd_p output is ‘1.’

Now, let’s build the 8-bit parity checker circuit.

The 8-bit parity checker circuit

Truth table

VHDL program

library ieee;
use ieee.std_logic_1164.all;
entity parity_chk is
      port( data:in bit_vector(7 downto 0);
                  p: in bit;
                  e: out bit);
end parity_chk;
architecture parity_arch of parity_chk is
signal temp : bit_vector(6 downto 0);
  begin
    temp(0)<=data(0) xor data(1);
    temp(1)<=temp(0) xor data(2);
    temp(2)<=temp(1) xor data(3);
    temp(3)<=temp(2) xor data(4);
    temp(4)<=temp(3) xor data(5);
    temp(5)<=temp(4) xor data(6);
    temp(6) <= temp(5) xor data(7);
    e <= p xor temp(6);
end parity_arch;

Simulation waveforms

Verify the ‘e’ output waveform with the parity input of ‘p’ and the data ‘D0-D7.’ For example, as highlighted in the diagram, for the input “0101 1011” and the parity ‘1,’ the error output is ‘1.’ For the input of “0100 1010” and the parity ‘0,’ the output is ‘0.’

In the next tutorial, we’ll learn how to design 8×3 encoder and 3×8 decoder circuits using the VHDL.