In **previous tutorial VHDL tutorial 3,** we have learned how to design, simulate, and verify any digital circuit in VHDL using Altera’s MAX+II VHDL simulator software.

*(If you are not following this VHDL tutorial series one by one, you are requested to go through all previous tutorials of these series before going ahead in this tutorial)*

In this tutorial,

- We shall write a VHDL program to build all digital gates
- Simulate the program to design digital circuit for all gates
- Verify the output waveform of program (digital circuit) with truth table of these logic GATES

Let us start with the digital circuit for which we shall write a VHDL program

__Digital Circuit__

Here is the truth table for the above circuit.

__Truth Table__Now we shall write a VHDL program, compile it, simulate it, and get the output in the form of the waveform. Finely, we shall verify those output waveforms with the given truth table.

*(Please go through step by step procedure given in previous tutorial (VHDL Tutorial 2) to create a project, edit and compile a program, create waveform file, simulate the program and generate output waveforms.)*

__VHDL Program
__library IEEE;

**use IEEE.STD_LOGIC_1164.ALL;**

**entity logic_gate is**

** Port ( A,B : in std_logic;**

** y_and,y_or,y_nand,y_nor,y_not,y_xor,y_xnor : out std_logic);**

**end logic_gate;**

**architecture all_gates of logic_gate is**

**begin**

** y_and <= a and b;**

** y_or <= a or b;**

** y_nand <= a nand b;**

** y_nor <= a nor b;**

** y_not <= not a ;**

** y_xor <= a xor b;**

** y_xnor <= a xnor b;**

**end all_gates;**

“*entity*” describes input-output connections of digital circuit. As per our circuit given above, we have only two inputs ‘A’ and ‘B’ and 7 outputs for 7 gates.

“*architecture*” describes the operation of the circuit – means how the output is generated from a given input.

*(To know more and get more details about VHDL program(s), please go through the first two tutorials VHDL tutorial 1 and VHDL tutorial 2 of these series.)*

Next, compile above program – create a waveform file with all inputs and outputs listed – simulate the project, and you will get the following result:

__Simulation Waveform__

Now verify these output waveforms with the truth table of GATEs. For example, here, one case is highlighted with inputs A=1 and B=1. You can verify the other three cases also.

This is how you can build a simple logic GATE circuit in VHDL and verify its output with their truth table.

In the **next tutorial**, we shall see how to build NAND, NOR, XOR, and XNOR gates using three basic gates AND, OR, and NOT using VHDL.