In previous tutorials VHDL tutorial (#6), we built a circuit for D Morgan’s Theorems in VHDL and verified its output to prove D Morgan’s theorems.
(If you are not following this VHDL tutorial series one by one, you are requested to go through all previous tutorials of these series before going ahead in this tutorial)
In this tutorial,
- We shall write a VHDL program to build all other gates (AND, OR, NOT, XOR, NOR, etc.) using only NAND gates
- Verify the output waveform of the program (digital circuit) with the truth table of AND, OR, NOT, XOR, NOR gates
(Please go through step by step procedure given in VHDL-tutorial 3 to create a project, edit and compile the program, create waveform file, simulate the program, and generate output waveforms.)
entity nand_uni_gate is
Port ( a,b : in std_logic;
y_not,y_and, y_or,, y_xor: out std_logic
architecture nand_uni_gate_arch of nand_uni_gate is
y_not <= a nand a;
y_and <= (a nand b) nand (a nand b);
y_or <= (a nand a) nand (b nand b);
y_nor <=((a nand a) nand (b nand b)) nand ((a nand a) nand (b nand b));
y_xor <= (a nand (a nand b)) nand (b nand (a nand b));
“entity” describes input-output connections of a digital circuit. As per our circuit given above, we have only two inputs ‘A’ and ‘B’ and five outputs for five circuits of different gates build using the NAND gate only.
“architecture” describes the operation of the circuit – means how the output is generated from a given input.
(To know more and get more details about VHDL program(s), please go through the first two tutorials VHDL tutorial 1 and VHDL tutorial 2 of these series.)
Next, compile above program – create waveform file with all inputs and outputs listed – simulate the project and you will get the following result
That means we can design all other gates using only the NAND gate, so the NAND gate is a universal gate.
In the next tutorial, we shall prove the NOR gate as a universal gate by designing AND, OR, NOT, NAND, and XNOR gates using only NOR gate.