What is Verilog, its features, and design flow?

Verilog is a hardware description language (HDL) first standardized by the Institute of Electrical and Electronics Engineers (IEEE) in 1995. It plays an essential role in electronic design automation (EDA) tools for designing and documenting digital systems.

Verilog is extensively used in the design and verification of digital circuits at various abstraction levels, from the transistor level to the system level.

The language describes digital systems — such as application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) — and supports various descriptions, including behavioral, register transfer level (RTL), and gate-level representations.

In this article, we’ll learn about the Verilog language, its features, application areas, design flow, modeling styles, and the difference between VHDL and Verilog.

Some of Verilog’s significant features are as follows.

Hierarchy: Verilog supports top-down and bottom-up design methodologies. You can define modules that can be nested within other modules.
Concurrency: In Verilog programming language, all statements within a module execute concurrently, making it suitable for modeling hardware.
Primitives: Verilog provides built-in primitives like gates, switches, and transmission gates.
Test benches: Verilog can be used to create test benches to verify the functionality of a design.
System tasks: Verilog includes a set of system tasks for testbench control, I/O operations, timing checks, and simulation control.

Verilog is not like other conventional programming languages. It’s a hardware description language (HDL), meaning it describes how hardware components are interconnected and how a complete circuit should behave (function).

Verilog versus VHDL

We previously covered a tutorial series on VHDL programming, and now will cover VLSI circuit designs, starting with VLSI design flow.

Many of you may be wondering:

“How do VHDL and Verilog languages differ?”
“Which one is better? Which is preferred?”
“Can they be used interchangeably?”

Both languages are HDL and are used to design, develop, and test digital circuits and systems. Each one has its own programming structures, styles, and advantages. However, VHDL was written as a description language, whereas Verilog was written as a hardware modeling language.
VHDL is a common choice in the aerospace and defense sectors, while Verilog is often preferred in the semiconductor industry.

Understanding these industry trends can help you make informed decisions about which language to use for your specific project.

Both languages have their own space and application areas. Anyone who wants to work in digital system design and chip design should have ample knowledge of both VHDL and Verilog programming languages. You can check the complete VHDL tutorial series here.

Verilog design flow

The specifications come first and describe the functionality, interface, and architecture of the digital IC circuit to be designed.
A behavioral description is then created to analyze the design in terms of its functionality, performance, compliance with given standards, and other specifications.
Once the RTL description is in place, EDA tools are typically used to take a design to the next level. These tools are instrumental in simulating and testing the circuit’s functionality, ensuring a reliable design process.
The RTL description is converted to a gate-level netlist using logic synthesis tools. A gate-level netlist describes the circuit in terms of the gates and connections between them, which are made to meet the timing, power, and area specifications.
The design is once again logically verified and tested. If any problems are found, it’s necessary to restart the process from the RTL description.
Once the design is deemed flawless, it’s time for the floor-planning process. Here, every component is strategically placed, including its’ routes and interconnections, ensuring the structural integrity of the circuit.
Lastly, a physical layout is created, which will be verified and then sent to fabrication.

Verilog modeling styles

Verilog supports several different modeling styles. Here are the three most popular:

Gate-level modeling
Dataflow modeling
Behavioral modeling

Let’s discuss them in detail with an example.

Gate-level modeling

This is the lowest level of abstraction in Verilog, where a design is described in terms of gates and their interconnections. Typically, this style is used for implementing and verifying small-scale designs or individual components within a more extensive system.

Example:

module and_gate(input a, b, output y);

and(y, a, b);

end module

In this example, the Verilog module “and_gate” is declared with two inputs, “a” and “b,” and an output “y.” The next statement, “and(y, a, b)” describes AND. The gate is implemented with one output and two inputs. The “and” is a gate primitive and innate to Verilog. Other primitives for gates, such as “or,” “nand,” “nor,” etc., are also provided in Verilog.

Dataflow modeling

In this style, the design is described in relation to the flow of data and the operations performed on that data. This is done using continuous assignments with the “assign” keyword. Dataflow modeling is more abstract than gate-level modeling and is typically used for describing combinational circuits.

Let’s look at the two input AND gate examples above using the dataflow modeling style.

module and_gate(input a, b, output b);

assign y = a & b;

end module

Behavioral modeling

This is the highest level of abstraction in Verilog. In behavioral modeling, the design is described in how it behaves. This style uses procedural statements (like if, case, for, while, etc.) enclosed within “always” or “initial” blocks. Behavioral modeling is typically used to describe complex control logic, verified using test benches.

Now, let’s view the same two input AND gate examples using the behavioral modeling style.

module and_gate(input a, b, output reg y);

always @(a, b)

begin

y = a & b;

end

end module

It’s worth noting that these modeling styles can be combined within the same design.

For example, there’s:

➢ Behavioral modeling to describe the overall behavior of a system
➢ Dataflow modeling to describe the data path
➢ Gate-level modeling to describe critical timing paths

The choice of modeling style depends on the requirements of the design and the stage of the design process.

In all the three modeling styles described above, there’s one commonality — the module. This module is not only a component, but it’s the fundamental building block of any Verilog program.

The Verilog module

A module is the principal design entity that can encapsulate any digital component, whether it’s a simple gate-level component or a complex design block.

A module in Verilog is a block of code with a specific functionality. It can represent a digital circuit or just a part of it. Each module has a unique name and can have several inputs and outputs. The internal function of the module is defined by continuous assignments, gate instantiations, and blocks.

Structure of Verilog module

module module_name (list_of_ports);

// Declarations

// Definitions

end module

module: The module is defined and declared by this keyword.
module_name: This is the name of the module. It should be unique and descriptive of the module’s functionality.
list_of_ports: These are the inputs and outputs of the module. They form the interface of the module with other modules.
Declarations: This section includes the declaration of all the internal wires and registers used in the module.
Definitions: This section includes the definition of the functionality of the module. It can include continuous assignments, gate instantiations, always blocks, initial blocks, etc.
end module: This indicates end of module block. It’s also a keyword.

Here’s an example:

module and_gate(input a, b, output b);

assign y = a & b;

end module

In this example, the:

“and_gate” is the name of the module
“a” and “b” are the inputs to the AND gate
“y” is the output from the AND gate
“assign y = a & b;” is the logic of the AND gate, which assigns the bitwise AND operation of inputs “a” and “b” to the output “y”
“input” and “output” keywords denote the direction and type of the ports
“assign” keyword is used to assign continuous values to the outputs based on the inputs.
“&” operator is the bitwise AND operator in the Verilog language.
“!” for the NOT operation and “|” for the OR operation are examples of other operators

A module can be instantiated in other modules, allowing for a hierarchical design methodology. It can be also used in test benches for simulation.

Next, here’s an example of a module instantiation:

module_name instance_name (list_of_connections);

module_name: This is the name of the module being instantiated
instance_name: This is the name of the instance. It should be unique within the parent module.
list_of_connections: These are the connections between the ports of the module and the wires/registers in the parent module.

This is an extremely basic module example. The Verilog modules can be more complex and can encapsulate an entire complex digital circuit. They can also include other modules, procedural blocks, and various control structures.

A module can include both structural and behavioral descriptions.

Structural descriptions are composed of instances of primitive gates or user-defined modules.
Behavioral descriptions use high-level constructs like loops, if-then-else statements, case statements, etc.

This flexibility makes Verilog a powerful language for hardware design and verification. The power of Verilog comes from this ability to build complex designs from simpler modules.

Verilog data types

Net data: These represent physical connections between structural elements and are used to model hardware behavior. Examples include wire, wand(wired-AND), wor(wired-OR), etc.
Register data: These hold values within procedural blocks of code. Examples include reg(register), integer, real, time, etc.
Vector data: Both net and register data types can be declared as vectors representing buses. For example, wire [7:0] data_bus; represents an 8-bit wire bus.
Memory data: Verilog supports multi-dimensional arrays known as memories. For example, reg [7:0] mem [0:255]; declares a 256-byte memory.
User-defined data (Enums): Verilog-2001 introduced the typedef and enum keywords to define custom data types.
Wire: is the most basic data type in Verilog. It connects different modules and does not retain its value.
Reg: This is not a physical register in the hardware but is used in procedural blocks and can retain its value until another is assigned to it.
Integer: This is a 32-bit data type that can hold an integer value, similar to the ‘int’ type in C/C++.
Real: This is used to represent floating-point numbers.
Time: This data type is used to represent simulation time.