COB IC : COB Manufacturing

COB MANUFACTURING

1. Substrate

There are a host of materials that are used, each with slightly different cost and performance features. The most commonly used board material is glass weave impregnated with epoxy, described as Flame Retardant (FR) number 4, or FR-4.

Following table lists traditional board laminate materials and their general properties.

	Basic Composition	General Properties
FR-1	Phenolic/Kraft paper	Excellent punching at room temperature Poor wet electrical properties
FR-2		Punchable at room temperature Extremely poor wet electrical properties
FR-3		Brittle, but punchable with heat
FR-4	Epoxy/Glass fabric	High flex and impact strength Excellent electrical properties Excellent for PTH applications
FR-5	Modified Epoxy/Glass fabric	Improved hot flex strength over FR-4 Excellent electrical properties
FR-6	Polyester/Glass material	Outstanding electrical properties Punchable at room temperature Higher flex strength than paper products
CRM-5	Polyester/Glass fabric surface Polyester/Glass paper core	Outstanding electrical properties Punchable at room temperature Double flex strength of FR-6
CRM-7		Same properties as FR-6 Smoother surface finish
CEM-1		Outstanding electrical properties Punchable at room temperature Double flex strength of FR-6
CEM-3		Harder than CEM-1 Good electrical properties Suitable for PTH applications
G-10	Epoxy/Glass fabric Non-flame retardant	Same as FR4

As Teflon exhibits good performance at higher temperatures, it is preferred for high temperature applications. For applications where temperature variations are very high, polyurethane is preferred.

In COB, tracks are normal copper tracks, but the bond pads are made from a Copper base covered with a layer of nickel and on top of it, a fine layer of gold is used.

The bond surface must be free from all contaminants, should have no distortions and unevenness should be very small.

2. Die Bonding

For bonding the die on a substrate, adhesives like silver epoxy pastes are used. The bonding process requires curing (after application of paste) and degassing at high temperature (150° C).

For dissipation of heat, chips are bonded to metallic plates (which are finally connected to heat sinks/casing) integrated on board.

3. Interconnections

There are three main types of chip bonding techniques used in semiconductor manufacturing industry:

· Flip Chip

Flip-chip bonding offers lower cost, increases package density while maintaining or improving circuit reliability. The flip-chip process wherein chip is assembled face down is ideal for size considerations because there is no extra need for contacts on the sides of the components. Performance is better due to reduced connection path; reliability is good due to lesser number of connections.

Flip chip is a wafer scale operation as all bonds are made at a time. Bumps are formed on the entire wafer and the wafer is diced; individual die are picked, fluxed and placed on the substrate. The flux must hold the die in place for handling through reflow. T

he solder must be melted above its melting point to form the interconnections. Underfill and encapsulation complete the assembly.

Wirebonding of bare die onto a laminate substrate is referred to as COB (chip on board), flip chip attach of a bare die to a laminate substrate is referred to as DCA (direct chip attach), flip-chip/ACF (anisotropic conductive film) attach of a bare die onto glass/LCD panels is called Chip-on-glass (COG).

· Tape Automated Bonding

Tape Automated Bonding uses a prefabricated carrier with copper leads adapted to the IC pads instead of single wires. The use of the term TCP (tape carrier package) has become a popular replacement for the term TAB

The metallurgy associated with TAB attach is complicated. The prefabricated carrier or tape consists of a perforated polyimide film. On this film is then glued a copper foil, and this copper is structured by photolithography like a flexible circuit. This process creates freestanding fingers in the tape openings, which are then soldered or welded to bumps previously created on the pads of the IC.

Tape may be removed afterwards. Ultimately, aluminum pads on the chip are attached to solder or gold pads on the substrate with a copper core lead frame going between them.

The precise time-temperature-pressure conditions at which the joint is formed will influence the intermetallics that form and the resulting reliability

TAB was almost forgotten due to wide adoption of wirebonding in semiconductor industry. However, it offers the advantage of higher package density (pad size are smaller by a factor of 2) and the advantage is being utilized by LCD drivers.

· Wirebonding

Wirebonding is the technique most widely used in most of the chips & is used for interconnections between the bond pads on a chip and bond pads on a substrate in COB technology. Wirebonding is best described as single point unit operation. Each bond is individually produced. Flexibility, Infrastructure and Cost are the major advantages of wirebonding.

Two types of wirebonding, viz. aluminium wire bonding and gold wire bonding are used.

Sl. No	Aluminium wire bonding	Gold wire bonding
1	Aluminium wirebonding is a friction welding process. Two metals are pressed (at predefined pressure) against each other, then vibrations using ultrasonic energy are provided until friction bond occurs	Gold wire bonding is a thermocompression bonding wherein combination of heat, pressure and ultrasonic energy welds the gold ball to the aluminum die pad
2	It is a pure ultrasonic welding process done at room temperature	Bonding of acceptable quality requires temperature in excess of 120° C
3	Bonding time is almost three times to that of gold wire bonding due to requirement of ultrasonic energy and vacuum chuck to hold the substrate	Bonding time is relatively less
4	Bond pad requires a fine layer of 0.1 mm gold over nickel covered copper base.	Bond pad requires a fine layer of 1 to 2 mm gold over nickel covered copper base.
5	Bonding tool used is generally wedge	Bonding tool used is capillary
6	Manufacturing Cost is relatively less	Manufacturing Cost is higher due to amount of gold used,
7	Suitable for plastic packages	Suitable for ceramic packages using Si-Au eutectic die attach but not for plastic packages(due to high temperatures)

The following figure show Aluminium Wirebonding in a memory module fabricated using COB.

4. Encapsulation

Encapsulation is done to protect the chip from the outside world. In addition, the protective package provides the electrical connections to act as interface with external signals.

ICs are available commercially in standard packages. These packages have specific form factor and pin count. Standard packages are available commercially in a limited number of forms and the number of connecting pins is also standardized. This can mean that one is compelled to select a much larger package even if only one extra electrical connection is required, which increases the size and cost unnecessarily. Chips with over 100 pins usually require expensive packages and sometimes the package geometry makes bonding more difficult which can result in damaged die. Special ASICs are usually produced in only small quantities with a corresponding increase in the difficulty of selecting a suitable package. The greatest difficulties lie in manufacturing custom specific packages with the largest possible pin counts.

COB technology offers the best solution in this case as a specific board design with the requisite number of interconnections can be generated in a very short time.

After wire bonding, the chip and all the bonds are encapsulated. The resulting package is perfectly matched to the requirements and cannot easily be copied which is often an advantage where intellectual property needs to be protected. Another benefit is that passive components and/or other chips can be integrated into the same package.

The advantage of this packaging method is the miniaturization that would not be possible with standard packages that are often 10 or 20 times larger than the die themselves. Secondly the cost of the standard packages with high pin count ASICs is often higher than the cost of the die themselves.

When compared with SMT, finished product using COB (or Hybrid) technology requires lesser process steps. This is depicted in the following figure: