N-bit gray counter using vhdl

This tutorial is about designing an N-bit gray counter in vhdl. I am using xilinx software tool to design and test the gray counter. So what is gray counter? A gray counter changes 1-bit only during one state to another state transition. The counter is same like the normal incremental counter. The only difference is in binary representation. Take a look at the below figure.

Binary to gray code state transition

In the above figure on the left side binary representation of the whole numbers starting from 0 and ending on 9 is shown. On the right hand side the equivalent of the binary to gray code is shown. Notice the difference only 1-bit changes between the gray code binary values.

Why N-bit gray counter

Its easy to design a fixed sized gray counter using case statement. But what if the size of the gray counter increases? With size of gray counter the vhdl code length increases which in any case is not feasible. So we have to come up with some cleaver and optimized methods to reduce vhdl code size and achieve greater speeds. An example of four bit gray counter with vhdl case statement is given below. Look at the size of code. What if it we increase it to 6-bit?

Gray counter with case statement

Gray code logic design in vhdl

Lets begin with our gray counter. I made an N-bit gray counter. Simulation results are shown below. For simulation we have to define the size of the counter i defined 6 bit. Verify the results below. Compare it with the above gray code figure.

N-bit gray counter in vhdl

Vhdl gray counter code

The main gray counter entity vhdl code is given below. The counter is designed on current and next state logic. I assume that you now what is meant by current state and next state logic. I also assume that you are well aware of FSM(finite state machine). If you don’t know about finite state machine and how it works? Then before moving any future i will suggest you to first take some tutorials on fine state machine and how it works?

In the main entity first a generic N: integer:=6 is defined. The generic variable is used to declare the size of the gray counter. In my case i want a 6-bit gray counter so i initialized it with 6. You can change it according to your need. Clock, reset and enable signals are input to the entity and the only output is our gray code. Notice that the output port size is dependent on the generic variable N. clock, reset and enable are 1-bit inputs.

In the architecture part few signals are defined. These signals are used to hold the values manipulated for gray counter by finite state machine. The reset is synchronous which means that reset execute on positive edge of the clock. In the absence of clock you cant reset the system.

Coming to the main and complex logic. How the gray counter is incremented in vhdl case?

Well the code part after process is generating the next gray code value for us. I am sure its not possible for me to write the logic for those three code statements which you can pick up and easily understand. I will give it a try.

After reset the current state value is 000000. We then xor this current state with the 5 lsb(least significant bits) of current state while concatenating the 0 at msb(most significant bit) of current state. & is concatenating operator. The result is placed in hold variable hold <= Currstate XOR (‘0’ & hold(N-1 DOWNTO 1));.

In the next statement we increment the hold by 1. The result is placed in next_hold variable next_hold <= std_logic_vector(unsigned(hold) + 1);.

In the third statement we perform the same concatenation and logical xor but this time on next_hold variable. The result is placed in Nextstate variable Nextstate <= next_hold XOR (‘0’ & next_hold(N-1 DOWNTO 1)); .

The current state is assigned to the output and next state is calculated. This next state is transferred to current state on next rising edge of clock.

Important: The above logic is hard to explain. But i bet you if you try to write them on paper and do the logic xor manually you can easily understand whats going on in.

6-bit gray counter main entity is shown below. The internal circuit is composed of xor gates flip flops and other components. The figure of internal components is huge and its not possible to show it in single picture so i removed it.

6-bit Gray Counter in vhdl

VHDL test bench

Gray counter test bench is simple. First the gray counter entity is instantiated as a component. Then few interconnect signals are defined. Two individual processes are part of the test bench. One process is dedicated to clock and the other is used for reset, enable and clock cycle delay purpose. Clock cycle is 20 ns.

In the above Vector_proc first the counter is reset. After reset the system waits for a rising edge of clock. Upon first rising edge reset is disabled and enable is activated. Soon after that the process goes in wait state and it waits until the next time it is reset. So this process is some what in halt state. The only process which is running continuously is clock process.

Project Files