Embedded Systems Power Optimization: Multi-Level Techniques

In the realm of embedded systems, power management plays a crucial role in determining both the design’s success and its overall performance. As energy efficiency becomes increasingly important in our technology-driven world, engineers and developers must consider power consumption at every stage of the design process. This article explores the various design levels where power reduction techniques can be effectively implemented, offering insights into creating more efficient and sustainable embedded systems.

Figure 1. A power-efficient embedded system includes hardware and software design and proper component selection.

Higher levels of power reduction techniques include system, algorithmic, and architectural levels, as well as lower levels of power reduction techniques, including circuit and process levels. The higher levels provide more significant amounts of power reduction for chip designs, giving designers a greater degree of freedom to implement low-power (up to 70 percent reduction) design techniques. Optimization is achieved by efficient implementation in different stages using these different techniques. Hence, the power optimization process is the most effective method for higher levels of abstraction.

Figure 2. Design flow levels.

System level
The system level generally includes the techniques implemented during customized ICs or hardware design manufacturing. The system-level techniques are the following:

Hardware/Software Partitioning. The mapping of a system level into specific hardware(FPGA, ASIC, etc.) and software(Code running on CPU, MCU, etc.) components based on their requirements.
Task characterization. This step helps develop a low-energy implementation strategy by characterizing tasks according to processing frequency, processing time, and hardware algorithm alternatives. This is important because the implementation strategies will depend heavily on these characteristics.

Algorithmic level
The most effective design decisions derive from choosing and optimizing algorithms at the highest levels so that the number of operations that require more considerable power is reduced. This approach also reduces the number of switching activities, which leads to a decrease in switched capacitance of the overall system, thus reducing the dynamic power consumption of the system. For example, arithmetic or register units of a microprocessor will perform only when such logic commands are invoked, so we can disable the logic commands that are not in use during a particular clock cycle.

Architectural level
Different techniques at the architectural level are applied to minimize dynamic power dissipation in arithmetic circuits, especially in digital multipliers. Some of the architectural-level techniques are:

Parallelism. Parallel processing involves the concurrent execution of several programs or blocks of a program. Parallelism can be achieved by multi-core architecture. By replicating the same core several times, the incoming inputs are applied to different cores in sequence.
Voltage Scaling. In this technique, the overall operating voltage of the device is kept low for the entire board, as power consumption is directly proportional to the operating voltage. For example, if all the chips can work on 2.7 V, then you would keep a margin of 1 V and set that voltage for the board. When the processor supply voltage is reduced, the system’s speed slows, but software techniques like pipelining can maintain the system’s throughput, as explained in the software techniques.
Pipelining. The process of accumulating instruction from the processor through a pipeline. It allows for storing and executing instructions in an orderly process. Pipelining does not reduce power by itself but reduces the critical path delay by inserting registers between combinational logic. Pipelining also reduces the instructions per clock cycle (IPC) due to high branch misprediction penalties and other hazards and thus can reduce energy efficiency. The timing slack from pipelining can be used for voltage scaling and gate downsizing to achieve significant power savings.

Logic and Circuit level
Logic and circuit levels generally include techniques that can be implemented during customized manufacturing of ICs or at the hardware and software design. Some of the logic and circuit-level techniques are:

Transistor sizing is the process of reducing or increasing the channel width of the transistor at the time of manufacturing. The smaller your transistors, the more transistors can fit on a chip, and the faster and more efficient the processor can be. For example, if the size of the transistor is 25 μm, then the drive current will be just 0.9mA, and if the size is 100 μmk, then the drive current will be 20mA.
Clock gating is a technique used in many synchronous circuits to reduce dynamic power dissipation by removing the clock signal when the circuit is not in use. This can be achieved by adding an Enable Circuit, which will pass the use of the clock when Enable is high and vice versa. These circuits can be a gate, tristate buffer, latch, etc.

Process/Technology level

Threshold Voltage. Reducing the voltage swing (swing is the difference between the maximum output voltage and minimum output voltage) and the effective load capacitance (sum of load capacitance and parasitic capacitance) reduces power dissipation. Also, reducing VDD in non-critical paths will help reduce power consumption.

Component Selection

Use more static than dynamic circuits, as the static power loss is significantly less in a dynamic logic circuit.
It is important to select the right input voltage for the embedded board, whether we are using a battery or an adapter for the power supply. For example, if all the circuitry on the board is powered by 5 V or 3.3 V, then using a 5 V to 6 V power input is better than using a 12/24 V DC input or battery input.
Boost circuits are generally inefficient. If buck conversion is an option, use buck instead of boost.
The quiescent current of a power supply is the amount of current that is consumed at zero or no load. Always use a low-quiescent current power supply, as it has very high efficiency at the current range your circuit consumes. (Figure 3)

Fig. 3: Quiescent Current power supply

Circuit Design Level The designer has several options while designing a low-power system, including the following:

Choose the low-power components in the design. For example, consider an IC with low power (active/idle) consumption and a low operating voltage rating when selecting an IC.
Optimize the size of the PCB so that you can minimize the power consumption of the electronic circuits.
The component should be placed so that signal track length can be minimized and signal propagation time is as fast as possible to minimize any power loss.

Low-power embedded system design offers several key benefits. Firstly, such systems generate less heat, which is advantageous for the environment. Additionally, the reduced power dissipation leads to an improved working cycle for the embedded system. Furthermore, low-power systems contribute to lower production costs, as they are typically simpler and more cost-effective to manufacture. These advantages make low-power embedded system design an attractive option for many applications.