VHDL Tutorial – 21: Designing an 8-bit, full-adder circuit using VHDL

Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial.

In the previous tutorial, VHDL Tutorial – 20, we learned how to design 4-bit binary-to-gray & gray-to-binary code converters by using VHDL.

In this tutorial, we will:

Write a VHDL program that builds an 8-bit, full-adder circuit
Verify the output waveform of the program (the digital circuit) with the circuit operation

The 8-bit, full-adder block diagram:

Now, let’s write, compile, and simulate a VHDL program. Then, we’ll get the waveform output and verify it.

Before starting, be sure to review the step-by-step procedure provided in VHDL Tutorial – 3 to design the project. It will ensure that you properly edit and compile the program and the waveform file, as well as the final output.

For this project, we’ve used a structural modeling style to build the 8-bit, full-adder circuit. A 1-bit, full-adder is used as the component.

VHDL program

library ieee;
use ieee.std_logic_1164.all;

entity FA_8bit is
port(x,y : in std_logic_vector(7 downto 0);
     cin : in std_logic;
     sum : out std_logic_vector(7 downto 0);
     co : out std_logic);
end FA_8bit;

architecture FA_arch of FA_8bit is
signal cary : std_logic_vector(6 downto 0);

component full_adder is
port (p,q,r:in std_logic; sm,cr: out std_logic);
end component;
begin
     a0:full_adder port map (x(0),y(0),cin,sum(0),cary(0));
     a1:full_adder port map (x(1),y(1),cary(0),sum(1),cary(1));
     a2:full_adder port map (x(2),y(2),cary(1),sum(2),cary(2));
     a3:full_adder port map (x(3),y(3),cary(2),sum(3),cary(3));
     a4:full_adder port map (x(4),y(4),cary(3),sum(4),cary(4));
     a5:full_adder port map (x(5),y(5),cary(4),sum(5),cary(5));
     a6:full_adder port map (x(6),y(6),cary(5),sum(6),cary(6));
     a7:full_adder port map (x(7),y(7),cary(6),sum(7),co);
end FA_arch;

library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port (p,q,r:in std_logic; sm,cr: out std_logic);
end full_adder;

architecture FA_arc of full_adder is
begin
    sm <= p xor q xor r;
    cr <= (p and q) or (q and r) or (r and p);
   end FA_arc;

It may help to review the first two VHDL tutorials (1 and 2) of this series to refresh you memory about how this works.

Next, compile the above program, creating and then saving a waveform file with all of the necessary inputs and outputs that are listed (ensuring you apply all of the different input combinations). Then, simulate the project. You should get the following result…

Simulation waveform