Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial.

In the previous tutorial, we designed a clocked SR latch circuits using VHDL (which is a very high-speed integrated circuit hardware description language).

For this project, we will:

• Write a VHDL program to build a D flip-flop circuit
• Verify the output waveform of the program (digital circuit) with the truth table of this flip flop circuit

The D flip flop circuit

Truth table

Now, let’s write, compile, and simulate a VHDL program. Then, we’ll get the output in waveform and verify it with the given truth table.

Before starting, be sure to review the step-by-step procedure provided in VHDL Tutorial – 3 to properly design the project, as well as edit and compile the program and the waveform file, including the final output.

For this tutorial, we’ve used a behavioral modeling style to write the VHDL program that will build the flip-flop circuit. This is the preferred modeling style for sequential digital circuits.

VHDL program

library ieee;
use ieee.std_logic_1164.all;
entity D_flip_flop is
    port (clk,Din : in std_logic;
             Q: out std_logic;
             Qnot : out std_logic);
 end D_flip_flop;
architecture DFF_arch of D_flip_flop is
    begin
        process (clk,Din)
          begin
           if(clk’event and clk=’1′) then
                 Q <= Din;
                 Qnot <= (not Din);
               end if;
        end process;
end DFF_arch;

To refresh your memory about how this works, go through the first two VHDL tutorials (1 and 2) of this series.

Next, compile the above program, creating a waveform file with all of the necessary inputs and outputs that are listed, and simulate the project. You should get the following result…

Simulation waveform

As shown in this figure, there are two cases highlighted in red and blue.

• Case 1: when clk=1 and Din=1  ->  Q = 1 and Qnot = 0
• Case 2: when clk=1 and Din = 0  ->  Q=0 and Qnot = 1

This program for the D flip flop circuit seems simple enough. So, let’s make it somewhat more complicated by adding two more input signals:

1. Reset: the active high reset input, so when the input is ‘1,’ the flip flop will be reset and Q=0, Qnot=1

2. Enable: enables the input for the flip flop circuit, so if it’s set to ‘0,’ the flip flop is disabled and both outputs are at high impedance (where ‘1’ is when the flip flop operates normally)

Truth table for the D flip flop

Now, here’s the program of the D flip flop with the enable and active high reset inputs.

library ieee;
use ieee.std_logic_1164.all;
entity D_flip_flop is
   port (clk,Din,rst,en : in std_logic;
            Q: out std_logic;
            Qnot : out std_logic);
 end D_flip_flop;
architecture DFF_arch of D_flip_flop is
   begin
       process (clk,en,Din,rest)
        begin
             if(en=’0′) then
               Q <=’z’;
               Qnot <= ‘z’;
              elsif(rst=’1′) then
               Q <=’0′;
               Qnot <=’1′;
              elsif(clk’event and clk=’1′) then
               Q <= Din;
               Qnot <= not Din;
             end  if;
     end process;
end DFF_arch;

When you compile and simulate above program you will get following waveform output…

Simulation waveforms

As shown in this figure, there are three highlighted cases in red, blue, and green.

• Case 1: when en = 0, both outputs Q and Qnot are high impedance (z)
• Case 2: when en=1 and rst=1 -> Q=0 and Qnot=1 (flip flop is reset)
• Case 3: when en=1, rst=0 and Din=1  -> Q=1 and Qnot=0

In next tutorial we’ll build a JK flip flop circuit using VHDL.

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Filed Under: Tutorials, VHDL, VHDL

 

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