Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial.

In the previous tutorial, VHDL Tutorial – 19, we designed a 4-bit binary counter using VHDL.

In this tutorial, we will:

• Write a VHDL program to build a 4-bit binary to gray, and gray to the binary code converter
• Verify the output waveform of program (digital circuit) with the truth table for the code converter

The 4-bit, binary-to-gray code converter

Truth table

Now, let’s write, compile, and simulate a VHDL program. Then, we’ll get the output in waveform and verify it with the given truth table.

Before starting, be sure to review the step-by-step procedure provided in VHDL Tutorial – 3 to design the project. It will ensure that you properly edit and compile the program and the waveform file, as well as the final output.

VHDL program

library ieee;
use ieee.std_logic_1164.all;

entity b2g_code is
port (b : in std_logic_vector(3 downto 0);
      g : out std_logic_vector(3 downto 0));
end b2g_code;

architecture b2g_arch of b2g_code is
 begin
g(3) <= b(3);
g(2) <= b(3) xor b(2);
g(1) <= b(2) xor b(1);
g(0) <= b(1) xor b(0);
  end b2g_arch;

It may help to review the first two VHDL tutorials (1 and 2) of this series to refresh you memory about how this works.

Next, compile the above program, creating and then saving a waveform file with all of the necessary inputs and outputs that are listed (ensuring you apply all of the different input combinations). Then, simulate the project. You should get the following result…

Simulation waveform

It’s easy to verify all of the different combinations of the binary code input (b0-b3) with the gray code output (g0 – g3). Next, let’s do the reverse procedure. We’ll build a gray-to-binary code converter circuit.

The gray-to-binary code converter circuit

VHDL program

library ieee;
use ieee.std_logic_1164.all;

entity g2b_code is
port (g : in std_logic_vector(3 downto 0);
      b : out std_logic_vector(3 downto 0));
end g2b_code;

architecture g2b_arch of g2b_code is
  begin
    b(3) <= g(3);
    b(2) <= g(3) xor g(2);
    b(1) <= g(3) xor g(2) xor g(1);
    b(0) <= g(3) xor g(2) xor g(1) xor g(0);
end g2b_arch;

Simulation waveforms

It’s clear from the figure that the gray code input (g0 – g3) and the binary code output (b0 – b3) matches with the given truth table.

In next tutorial, we’ll build an 8-bit, full-adder circuit using VHDL.

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Filed Under: Tutorials, VHDL, VHDL

 

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